CY7C1360B View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1360B Datasheet PDF : 34 Pages
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CY7C1360B
CY7C1362B
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
TAP Timing
1
2
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
3
4
5
6
Test Clock
(TCK)
Test Mode Select
(TMS)
tTH
tTL
tTMSS tTMSH
tCYC
tTDIS tTDIH
Test Data-In
(TDI)
Test Data-Out
(TDO)
tTDOV
tTDOX
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Description
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
tTL
TCK Clock LOW time
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
tTDIS
TDI Set-up to TCK Clock Rise
tCS
Capture Set-up to TCK Rise
Hold Times
tTMSH
TMS hold after TCK Clock Rise
tTDIH
TDI Hold after Clock Rise
tCH
Capture Hold after Clock Rise
Notes:
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1ns.
Min.
50
25
25
0
5
5
5
5
5
5
Document #: 38-05291 Rev. *C
Max.
20
5
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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