CY8C20160-LDX1I View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY8C20160-LDX1I Datasheet PDF : 46 Pages
| |||
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Typical Circuits (continued)
Figure 6. Circuit 3 – Compatibility with 1.8 V I2C Signaling [8, 9]
Figure 7. Circuit 4 – Powering Down CapSense Express Device for Low Power Requirements [10]
Output
enable
LDO
Output
VDD
LED
I2C Pull
UPs
Master
Or
Host
CapSense Express SDA
SCL
I2C
BUS
Notes
8. 1.8 V VDD_I2C VDD_CE and 2.4 V VDD_CE 5.25 V.
9. The I2C drive mode of the CapSense device should be configured properly before using in an I2C environment with external pull-ups. Please refer to I2C_ADDR_DM
register and its factory setting.
10.
Fshoor uloldwbpeofwroemr rtehqeuisraemmeenstosu, rifcVeDsDucish
to be turned
that turning
driven high by the master in this situation. If a port
off, this concept can be
off the
pin or
gVrDoDupeonfsuproerst
that
pins
used. The requirement is that the
no signal is applied to the device
wVDhDiles
of CapSense Express, I2C pull-ups, and LEDs
it is unpowered. The I2C signals should not be
of the master can cater to the power supply requirements of the circuit, the LDO can be
avoided.
Document Number: 001-54606 Rev. *J
Page 7 of 46
Share Link: 