CY8C20160-LDX1I View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY8C20160-LDX1I Datasheet PDF : 46 Pages
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CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
I2C Interface
The CapSense Express devices support the industry standard I2C protocol, which can be used for:
■ Configuring the device
■ Reading the status and data registers of the device
■ Controlling device operation
■ Executing commands
The I2C address can be modified during configuration.
I2C Device Addressing
The device uses a seven bit addressing protocol. The I2C data transfer is always initiated by the master sending a one byte address:
the first 7 bits contain the address and the LSB indicates the data transfer direction. Zero in the LSB bit indicates the write transaction
from master and one indicates read transfer by the master. The following table shows examples for different I2C addresses.
Table 1. I2C Address Examples
7-bit Slave Address
1
1
75
75
D7
D6
D5
D4
D3
D2
D1
D0
8-bit Slave Address
0
0
0
0
0
0
1
0(W)
02
0
0
0
0
0
0
1
1(R)
03
1
0
0
1
0
1
1
0(W)
96
1
0
0
1
0
1
1
1(W)
97
I2C Clock Stretching
‘Clock stretching’ or ‘bus stalling’ in I2C communication protocol
is a state in which the slave holds the SCL line low to indicate
that it is busy. In this condition, the master is expected to wait till
the SCL is released by the slave.
When an I2C master communicates with the CapSense Express
device, the CapSense Express stalls the I2C bus after the
reception of each byte (that is, just before the ACK/NAK bit) until
processing of the byte is complete and critical internal functions
are executed. Use a fully I2C compliant master to communicate
with the CapSense Express device.
If the I2C master does not support clock stretching (a bit banged
software I2C Master), the master must wait for a specific amount
of time (as specified in Format for Register Write and Read on
page 9) for each register write and read operation before the next
bit is transmitted. The I2C master must check the SCL status (it
should be high) before the I2C master initiates any data transfer
with CapSense Express. If the master fails to do so and
continues to communicate, the communication is erroneous.
The following diagrams represent the ACK time delays shown in
Format for Register Write and Read on page 9 for write and read.
Document Number: 001-54606 Rev. *J
Page 8 of 46
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