DSP56KFAMUM/AD(1996) View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56KFAMUM/AD
(Rev.:1996)

24-BIT DIGITAL SIGNAL PROCESSOR

Motorola => Freescale 

Design Considerations

Host Port Considerations

CANCELLING A PENDING HOST COMMAND EXCEPTION

The host processor may elect to clear the HC bit to cancel the Host Command

Exception request at any time before it is recognized by the DSP. Because the host

does not know exactly when the exception will be recognized (due to exception

processing synchronization and pipeline delays), the DSP may execute the Host

Command Exception after the HC bit is cleared. For these reasons, the HV bits must

not be changed at the same time the HC bit is cleared.

VARIANCE IN THE HI TIMING

HI timing may vary during initial startup during the time after reset before the PLL

locks. Therefore, before a host attempt to load (i.e., bootstrap) the DSP, the host

should first make sure that the HI port programming has been completed. The

following steps can be used to ensure that the programming is complete:

1. Set the INIT bit in the ICR

2. Poll the INIT bit until it is cleared.

3. Read the ISR.

An alternate method is:

1. Write the TREQ/RREQ together with INIT.

2. Poll INIT, ISR, and the HREQ pin.

DSP Programming Considerations

SYNCHRONIZATION OF STATUS BITS FROM HOST TO DSP

DMA, HF1, HF0, and HCP, HTDE, and HRDF status bits are set or cleared by the host

processor side of the interface. These bits are individually synchronized to the DSP

clock.

Note: Refer to DSP56002 User’s Manual sections describing the I/O Interface and

Host/DMA Interface Programming Model for descriptions of these status

bits.

READING HF0 AND HF1 AS AN ENCODED PAIR

A potential problem exists when reading status bits HF0 and HF1 as an encoded pair

(i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small

probability exists that the DSP will read the status bits synchronized during

transition. The solution to this potential problem is to read the HF0 and HF1 bits

twice and check for consensus.

MOTOROLA

DSP56002/D, Rev. 3

4-7

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