DSP56KFAMUM/AD(1996) View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56KFAMUM/AD Datasheet PDF : 110 Pages
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Signal/Pin Descriptions
PLL and Clock
PLL AND CLOCK
Table 1-4 PLL and Clock Signals
Signal
Name
EXTAL
XTAL
CKOUT
Signal
Type
Input
Output
Output
State
during
Reset
Signal Description
Input
Chip-
driven
Chip-
driven
External Clock/Crystal Input—This input connects the internal
oscillator input to an external crystal or to an external oscillator.
Crystal Output—This output connects the internal crystal oscillator
output to an external crystal. If an external oscillator is used, XTAL
should be left unconnected.
PLL Output Clock—When the PLL is enabled and locked, this
signal provides a 50% duty cycle output clock signal synchronized
to the internal processor clock.
When the PLL is enabled and the Multiplication Factor is less than
or equal to 4, then CKOUT is synchronized to EXTAL.
When the PLL is disabled, the output clock at CKOUT is derived
from, and has the same frequency and duty cycle as, EXTAL.
CKP
PCAP
Input
Input/
Output
Note: For information about using the PLL Multiplication Factor,
see the DSP56002 User’s Manual.
Input
PLL Output Clock Polarity Control—The value of this signal at
reset defines the polarity of the CKOUT output relative to EXTAL. If
CKP is pulled low by connecting through a resistor to ground,
CKOUT and EXTAL have the same polarity. Pulling CKP high by
connecting it through a resistor to VCC causes CKOUT and EXTAL
to be inverse polarities. The polarity of CKOUT is latched at the end
of reset; therefore, any changes to CKP after deassertion of RESET
do not affect CKOUT polarity.
Indeter-
minate
PLL Capacitor—This signal is used to connect the required external
filter capacitor to the PLL filter. Connect one end of the capacitor to
PCAP and the other to VCCP. The value of the capacitor is specified
in Section 2 of this data sheet.
MOTOROLA
DSP56002/D, Rev. 3
1-5
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