DSP56307UM View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56307UM

24-BIT DIGITAL SIGNAL PROCESSOR

Motorola => Freescale 

Signals/Connections

Interrupt and Mode Control

INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the chipÕs operating mode as it comes out

of hardware reset. After RESET is deasserted, these inputs are hardware interrupt

request lines.

Table 1-9 Interrupt and Mode Control

Signal Name

Type

State During

Reset

Signal Description

RESET

Input Input

ResetÑRESET is an active-low, Schmitt-trigger input.

Deassertion of RESET is internally synchronized to

CLKOUT. When asserted, the chip is placed in the

Reset state and the internal phase generator is reset.

The Schmitt-trigger input allows a slowly rising input

(such as a capacitor charging) to reset the chip

reliably. If RESET is deasserted synchronous to

CLKOUT, exact start-up timing is guaranteed,

allowing multiple processors to start synchronously

and operate together in Òlock-step.Ó When the RESET

signal is deasserted, the initial chip operating mode is

latched from the MODA, MODB, MODC, and MODD

inputs. The RESET signal must be asserted after

power up.

MODA

Input Input

Mode Select AÑMODA is an active-low

Schmitt-trigger input, internally synchronized to

CLKOUT. MODA, MODB, MODC, and MODD select

one of 16 initial chip operating modes, latched into the

OMR when the RESET signal is deasserted.

IRQA

Input

External Interrupt Request AÑAfter reset, this input

becomes a level-sensitive or negative-edge-triggered,

maskable interrupt request input during normal

instruction processing. If IRQA is asserted

synchronous to CLKOUT, multiple processors can be

resynchronized using the WAIT instruction and

asserting IRQA to exit the wait state. If the processor is

in the stop standby state and IRQA is asserted, the

processor will exit the stop state.

Not Recommended for New Design

MOTOROLA

DSP56307 Technical Data

1-11

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