DSP56309/D View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56309/D

24-Bit Digital Signal Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

Host Interface (HI08)

1.8 Host Interface (HI08)

The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08 supports

a variety of standard buses and connects directly to a number of industry-standard microcomputers,

microprocessors, DSPs, and DMA hardware.

1.8.4

Host Port Usage Considerations

Careful synchronization is required when the system reads multiple-bit registers that are written by

another asynchronous system. This is a common problem when two asynchronous systems are connected

(as they are in the Host port). The considerations for proper operation are discussed in Table 1-10.

Table 1-10. Host Port Usage Considerations

Action

Description

Asynchronous read of receive

byte registers

When reading the receive byte registers, Receive register High (RXH), Receive

register Middle (RXM), or Receive register Low (RXL), use interrupts or poll the

Receive register Data Full (RXDF) flag that indicates data is available. This assures

that the data in the receive byte registers is valid.

Asynchronous write to transmit

byte registers

Do not write to the transmit byte registers, Transmit register High (TXH), Transmit

register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register

Data Empty (TXDE) bit is set indicating that the transmit byte registers are empty.

This guarantees that the transmit byte registers transfer valid data to the Host

Receive (HRX) register.

Asynchronous write to host

vector

Change the Host Vector (HV) register only when the Host Command bit (HC) is

clear. This practice guarantees that the DSP interrupt control logic receives a stable

vector.

1.8.5

Host Port Configuration

HI08 signal functions vary according to the programmed configuration of the interface as determined by

the 16 bits in the HI08 Port Control Register.

Table 1-11. Host Interface

Signal Name

Type

State During

Reset1,2

Signal Description

H[0–7]

Input/Output

Ignored Input Host Data—When the HI08 is programmed to interface with a

non-multiplexed host bus and the HI function is selected, these

signals are lines 0–7 of the bidirectional Data bus.

HAD[0–7]

Input/Output

Host Address—When the HI08 is programmed to interface with a

multiplexed host bus and the HI function is selected, these signals

are lines 0–7 of the bidirectional multiplexed Address/Data bus.

PB[0–7]

Input or Output

Port B 0–7—When the HI08 is configured as GPIO through the

HI08 Port Control Register, these signals are individually

programmed as inputs or outputs through the HI08 Data Direction

Register.

1-9

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