DSP56309/D View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56309/D Datasheet PDF : 112 Pages
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Freescale Semiconductor, Inc.
Enhanced Synchronous Serial Interface 1 (ESSI1)
Table 1-13. Enhanced Serial Synchronous Interface 1 (Continued)
Signal Name Type
SC12
Input/Output
State During
Reset1,2
Signal Description
Ignored Input
Serial Control Signal 2—The frame sync for both the transmitter
and receiver in synchronous mode and for the transmitter only in
asynchronous mode. When configured as an output, this signal is
the internally generated frame sync signal. When configured as an
input, this signal receives an external frame sync signal for the
transmitter (and the receiver in synchronous operation).
PD2
SCK1
Input or Output
Port D 2—The default configuration following reset is GPIO input
PD2. When configured as PD2, signal direction is controlled
through the Port D Direction Register. The signal can be
configured as an ESSI signal SC12 through the Port D Control
Register.
Input/Output
Ignored Input
Serial Clock—Provides the serial bit rate clock for the ESSI. The
SCK1 is a clock input or output used by both the transmitter and
receiver in synchronous modes or by the transmitter in
asynchronous modes.
Although an external serial clock can be independent of and
asynchronous to the DSP system clock, it must exceed the
minimum clock cycle time of 6T (that is, the system clock
frequency must be at least three times the external ESSI clock
frequency). The ESSI needs at least three DSP phases inside
each half of the serial clock.
PD3
SRD1
Input or Output
Port D 3—The default configuration following reset is GPIO input
PD3. When configured as PD3, signal direction is controlled
through the Port D Direction Register. The signal can be
configured as an ESSI signal SCK1 through the Port D Control
Register.
Input
Ignored Input Serial Receive Data—Receives serial data and transfers the data
to the ESSI Receive Shift Register. SRD1 is an input when data is
being received.
PD4
STD1
Input or Output
Port D 4—The default configuration following reset is GPIO input
PD4. When configured as PD4, signal direction is controlled
through the Port D Direction Register. The signal can be
configured as an ESSI signal SRD1 through the Port D Control
Register.
Output
Ignored Input Serial Transmit Data—Transmits data from the Serial Transmit
Shift Register. STD1 is an output when data is being transmitted.
PD5
Input or Output
Port D 5—The default configuration following reset is GPIO input
PD5. When configured as PD5, signal direction is controlled
through the Port D Direction Register. The signal can be
configured as an ESSI signal STD1 through the Port D Control
Register.
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, the signal is tri-stated.
2. The Wait processing state does not affect the signal state.
3. All inputs are 5 V tolerant.
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