DSP56311UM/D View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56311UM/D

24-Bit Digital Signal Processor

Motorola => Freescale 

Power Consumption Benchmark

A-10

M_FDBA EQU

M_FCBA EQU

M_FDCH EQU

$FFFFB6

$FFFFB7

$FFFFB8

; EFCOP Data Base Address

; EFCOP Coefficient Base Address

; EFCOP Decimation/Channel Register

;------------------------------------------------------------------------

;

;

EQUATES for Phase Locked Loop (PLL)

;

;------------------------------------------------------------------------

;

Register Addresses Of PLL

M_PCTL EQU $FFFFFD

; PLL Control Register

;

PLL Control Register

M_MF EQU $FFF : Multiplication Factor Bits Mask (MF0-MF11)

M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2)

M_XTLR EQU 15 ; XTAL Range select bit

M_XTLD EQU 16 ; XTAL Disable Bit

M_PSTP EQU 17 ; STOP Processing State Bit

M_PEN EQU 18 ; PLL Enable Bit

M_PCOD EQU 19 ; PLL Clock Output Disable Bit

M_PD EQU $F00000; PreDivider Factor Bits Mask (PD0-PD3)

;------------------------------------------------------------------------

;

;

EQUATES for BIU

;

;------------------------------------------------------------------------

;

Register Addresses Of BIU

M_BCR EQU $FFFFFB; Bus Control Register

M_DCR EQU $FFFFFA; DRAM Control Register

M_AAR0 EQU $FFFFF9; Address Attribute Register 0

M_AAR1 EQU $FFFFF8; Address Attribute Register 1

M_AAR2 EQU $FFFFF7; Address Attribute Register 2

M_AAR3 EQU $FFFFF6; Address Attribute Register 3

M_IDR EQU $FFFFF5 ; ID Register

;

Bus Control Register

M_BA0W EQU $1F ; Area 0 Wait Control Mask (BA0W0-BA0W4)

M_BA1W EQU $3E0; Area 1 Wait Control Mask (BA1W0-BA14)

M_BA2W EQU $1C00; Area 2 Wait Control Mask (BA2W0-BA2W2)

M_BA3W EQU $E000; Area 3 Wait Control Mask (BA3W0-BA3W3)

M_BDFW EQU $1F0000 ; Default Area Wait Control Mask (BDFW0-BDFW4)

M_BBS EQU 21 ; Bus State

M_BLH EQU 22 ; Bus Lock Hold

M_BRH EQU 23 ; Bus Request Hold

;

DRAM Control Register

M_BCW EQU $3 ; In Page Wait States Bits Mask (BCW0-BCW1)

M_BRW EQU $C ; Out Of Page Wait States Bits Mask (BRW0-BRW1)

M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1)

M_BPLE EQU 11 ; Page Logic Enable

M_BME EQU 12 ; Mastership Enable

M_BRE EQU 13 ; Refresh Enable

M_BSTR EQU 14 ; Software Triggered Refresh

M_BRF EQU $7F8000; Refresh Rate Bits Mask (BRF0-BRF7)

M_BRP EQU 23 ; Refresh prescaler

;

Address Attribute Registers

M_BAT EQU $3 ; Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1)

M_BAAP EQU 2 ; Address Attribute Pin Polarity

M_BPEN EQU 3 ; Program Space Enable

M_BXEN EQU 4 ; X Data Space Enable

M_BYEN EQU 5 ; Y Data Space Enable

M_BAM EQU 6 ; Address Muxing

M_BPAC EQU 7 ; Packing Enable

M_BNC EQU $F00 ; Number of Address Bits to Compare Mask (BNC0-BNC3)

M_BAC EQU $FFF000; Address to Compare Bits Mask (BAC0-BAC11)

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