DSP56100 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56100

16-bit General Purpose Digital Signal Processor

Motorola => Freescale 

PRELIMINARY - 6/15/93

Layout Practices

Each DSP56166 Vdd pin should be provided with a low-impedance path to + 5 volts. Each DSP56166 Vss

pin should likewise be provided with a low-impedance path to ground. The power supply pins drive six dis-

tinct groups of logic on chip. They are:

Power and Ground Connections for CQFP and PQFP

Vdd

33,96

92,103

4,15

36

59,76

23

Vss

Function

47,104

89,95,101,108

1,7,12,18

38

53,73,79

26

Internal Logic supply pins

Address bus output buffer supply pins

Data bus output buffer supply pins

Bus control buffer supply pins

OnCE, Port B and C output buffer supply pins

Codec analog supply pins

Power and Ground Connections

The VDD power supply should be bypassed to ground using at least six 0.01-0.1 uF bypass capacitors lo-

cated either underneath the chip’s socket or as close as possible to the four sides of the package. The ca-

pacitor leads and associated printed circuit traces connecting to chip Vdd and Vss should be kept to less

than 1/2” per capacitor lead. The use of at least a four layer board is recommended, employing two inner

layers as Vdd and Vss planes. All output pins on the DSP56166 have fast rise and fall times. Printed circuit

(PC) trace interconnection length should be minimized in order to minimize undershoot and reflections

caused by these fast output switching times. This recommendation particularly applies to the address and

data buses as well as the PS/DS, BS, RD, WR, R/W, PEREN, IRQA, IRQB, and HEN pins. Maximum PC

trace lengths on the order of 6" are recommended. Capacitance calculations should consider all device

loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing

becomes especially critical in systems with higher capacitive loads because these loads create higher tran-

sient currents in the Vdd and Vss circuits.

The analog power for the VDDA pin and the analog ground for the VSSA pin should be separated from the

digital VDD and ground planes. The analog power and ground planes should only be tied to the digital power

and ground planes at one point where current enters and exits only at this point.

The analog VDD and ground planes should not have digital signal running over them if possible. The analog

VDD and ground pins should be decoupled as close to the DSP as possible.

Clocks signals should not be run across many signals and should be kept away from analog power and

ground signals as well as any analog signals.

Refer to Analog I/O Figure 1. for more details.

MOTOROLA

DSP56166 Technical Data Sheet

4

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