DSP56004 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56004 Datasheet PDF : 82 Pages
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Freescale Semiconductor, Inc.
Signal/Connection Descriptions
Serial Host Interface (SHI)
SERIAL HOST INTERFACE (SHI)
The Serial Host Interface (SHI) has five I/O signals, which may be configured to
operate in either SPI or I2C mode. Table 1-8 lists the SHI signals.
Signal Name
SCK
SCL
Table 1-8 Serial Host Interface (SHI) signals
Signal
Type
State
during
Reset
Signal Description
Input or
Output
Input or
Output
Tri-stated
SPI Serial Clock (SCK)—The SCK signal is an output
when the SPI is configured as a master, and a Schmitt-
trigger input when the SPI is configured as a slave. When
the SPI is configured as a master, the SCK signal is
derived from the internal SHI clock generator. When the
SPI is configured as a slave, the SCK signal is an input,
and the clock signal from the external master
synchronizes the data transfer. The SCK signal is ignored
by the SPI if it is defined as a slave and the Slave Select
(SS) signal is not asserted. In both the master and slave
SPI devices, data is shifted on one edge of the SCK signal
and is sampled on the opposite edge where data is stable.
Edge polarity is determined by the SPI transfer protocol.
I2C Serial Clock (SCL)—SCL carries the clock for bus
transactions in the I2C mode. SCL is a Schmitt-trigger
input when configured as a slave, and an open-drain
output when configured as a master. SCL should be
connected to VCC through a pull-up resistor. The
maximum allowed internally generated bit clock
fIr2eCqmueondceywishFeorsec/F4osfoc risththeeScPlIomckoodne
and Fosc/6 for
EXTAL. The
the
maximum allowed externally generated bit clock
frequency
I2C mode.
is Fosc/3 for the SPI mode and
This signal is tri-stated during
Fosc/5 for the
hardware reset,
software reset, or individual reset (no need for external
pull-up in this state).
1-10
DSP56004/D, Rev. 3
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