DSP56004 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56004

SYMPHONY™ AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS

Freescale Semiconductor 

Freescale Semiconductor, Inc.

Signal/Connection Descriptions

Serial Host Interface (SHI)

Signal Name

SS

HA2

HREQ

Table 1-8 Serial Host Interface (SHI) signals (Continued)

Signal

Type

State

during

Reset

Signal Description

Input

Input

Tri-stated

SPI Slave Select (SS)—This signal is an active low

Schmitt-trigger input when configured for the SPI

mode. When configured for the SPI Slave mode, this

signal is used to enable the SPI slave for transfer.

When configured for the SPI Master mode, this

signal should be kept deasserted. If it is asserted

while configured as SPI master, a bus error

condition will be flagged.

I2C Slave Address 2 (HA2)—This signal uses a

Schmitt-trigger input when configured for the I2C

mode. When configured for the I2C Slave mode, the

HA2 signal is used to form the slave device address.

HA2 is ignored in the I2C Master mode. If SS is

deasserted, the SHI ignores SCK clocks and keeps

the MISO output signal in the high-impedance

state.

Input or

Output

Note:

This signal is tri-stated during hardware reset,

software reset, or individual reset (no need for

external pull-up in this state).

Tri-stated

Host Request—This signal is an active low Schmitt-

trigger input when configured for the Master mode, but

an active low output when configured for the Slave

mode. When configured for the Slave mode, HREQ is

asserted to indicate that the SHI is ready for the next data

word transfer and deasserted at the first clock pulse of

the new data word transfer. When configured for the

Master mode, HREQ is an input and when asserted by

the external slave device, it will trigger the start of the

data word transfer by the master. After finishing the data

word transfer, the master will await the next assertion of

HREQ to proceed to the next transfer.

Note:

This signal is tri-stated during hardware, software,

individual reset, or when the HREQ[1:0] bits (in the

HCSR) are cleared (no need for external pull-up in this

state).

1-12

DSP56004/D, Rev. 3

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