AC Electrical Characteristics
A[0–17]
DMA Source Address
RD
2.4.5
WR
IRQA, IRQB,
IRQC, IRQD,
NMI
29
First Interrupt Instruction Execution
Figure 2-9. External Memory Access (DMA Source) Timing
External Memory Expansion Port (Port A)
2.4.5.1 SRAM Timing
Table 2-8. SRAM Timing
No.
Characteristics
100 Address valid and AA assertion pulse width2
101 Address and AA valid to WR assertion
102 WR assertion pulse width
103 WR deassertion to address not valid
104 Address and AA valid to input data valid
105 RD assertion to input data valid
106 RD deassertion to data not valid (data hold time)
107 Address valid to WR deassertion2
108 Data valid to WR deassertion (data set-up time)
109 Data hold time from WR deassertion
110 WR assertion to data active
Symbol
tRC, tWC
tAS
tWP
tWR
tAA, tAC
tOE
tOHZ
tAW
tDS (tDW)
tDH
—
Expression1
(WS + 2) × TC −4.0
[2 ≤WS ≤7]
(WS + 3) × TC −4.0
[WS ≥ 8]
0.75 × TC – 3.0
[2 ≤WS ≤3]
1.25 × TC – 3.0
[WS ≥ 4]
WS × TC −4.0
[2 ≤WS ≤3]
(WS −0.5) × TC −4.0
[WS ≥ 4]
1.25 × TC −4.0
[2 ≤WS ≤7]
2.25 × TC −4.0
[WS ≥ 8]
(WS + 0.75) × TC −6.5
[WS ≥ 2]
(WS + 0.25) × TC −6.5
[WS ≥ 2]
(WS + 0.75) × TC −4.0
[WS ≥ 2]
(WS −0.25) × TC −5.4
[WS ≥ 2]
1.25 × TC −4.0
[2 ≤WS ≤7]
2.25 × TC −4.0
[WS ≥ 8]
0.25 × TC −4.0
[2 ≤WS ≤3]
–0.25 × TC −4.0
[WS ≥ 4]
Freescale Semiconductor
DSP56311 Technical Data, Rev. 8
150 MHz
Min Max
22.7
Unit
ns
69.3
—
ns
2.0
—
ns
5.3
—
ns
9.3
—
ns
19.3
—
ns
4.3
—
ns
11.0
—
ns
—
11.8 ns
—
8.5
ns
0.0
—
ns
14.3
—
ns
6.3
—
ns
4.3
—
ns
11.0
—
ns
–2.4
—
ns
–5.7
—
ns
2-11