Index
A
ac electrical characteristics 4
B
Boundary Scan (JTAG Port) timing diagram 54
bus
external address 4
external data 4
out of page and refresh timings
11 wait states 31
15 wait states 33
4 wait states 27
8 wait states 29
Page mode
read accesses 26
wait states selection guide 17
write accesses 25
Page mode timings
1 wait state 17
2 wait states 20
3 wait states 22
4 wait states 23
refresh access 37
C
E
Clock 4
clock
external 4
operation 6
clocks
internal 4
configuration 3
D
dc electrical characteristics 3
design considerations
electrical 3
PLL 4
power consumption 3
thermal 1
DRAM
out of page
wait states selection guide 27
electrical design considerations 3
emory 3
Enhanced Serial Audio Interface 9
ESAI 9
receiver timing 51, 52
timings 47
transmitter timing 50
EXTAL jitter 4
external address bus 4
external bus control 4, 5
external clock operation 4
external data bus 4
external interrupt timing (negative edge-triggered)
11
external level-sensitive fast interrupt timing 10
external memory access (DMA Source) timing 12
External Memory Expansion Port 4, 12
Freescale Semiconductor
DSP56364 Technical Data, Rev. 4.1
Index-1