read and write accesses 12
Stop state
recovery from 11, 12
Stop timing 7
supply voltage 2
T
Test Access Port timing diagram 55
Test Clock (TCLK) input timing diagram 54
thermal characteristics 2
thermal design considerations 1
Timing
Enhanced Serial Audio Interface (ESAI) 50
General Purpose I/O (GPIO) Timing 47
OnCE™ (On Chip Emulator) Timing 47
Serial Host Interface (SHI) SPI Protocol Tim-
ing 37
Serial Host Interface (SHI) Timing 37
timing
interrupt 7
mode select 7
Reset 7
Stop 7
TQFP
pin list by number 3
pin-out drawing (top) 1
Freescale Semiconductor
DSP56364 Technical Data, Rev. 4.1
Index-3