DSP56300FM View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56300FM Datasheet PDF : 148 Pages
| |||
Reset, Stop, Mode Select, and Interrupt Timing
3.9 Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1
No.
Characteristics
Expression2
8 Delay from RESET assertion to all pins at reset value3
—
9 Required RESET duration4
• Power on, external clock generator, PLL disabled
50 × ETC
• Power on, external clock generator, PLL enabled
1000 × ETC
• Power on, internal oscillator
75000 × ETC
• During STOP, XTAL disabled (PCTL Bit 16 = 0)
75000 × ETC
• During STOP, XTAL enabled (PCTL Bit 16 = 1)
2.5 × TC
• During normal operation
2.5 × TC
10 Delay from asynchronous RESET deassertion to first
external address output (internal reset deassertion)5
• Minimum
3.25 × TC + 2.0
• Maximum
20.25 TC + 7.50
13 Mode select setup time
Min Max Unit
— 26.0 ns
500.0 —
ns
10.0 —
ns
0.75 —
μs
0.75 — ms
25.0 — ms
25.0 —
ns
34.5 —
ns
— 211.5 ns
30.0 — ns
14 Mode select hold time
0.0
—
ns
15 Minimum edge-triggered interrupt request assertion width
6.6
—
ns
16 Minimum edge-triggered interrupt request deassertion width
6.6
—
ns
17 Delay from IRQA, IRQB, IRQD, NMI assertion to external
memory access address out valid
• Caused by first interrupt instruction fetch
• Caused by first interrupt instruction execution
18 Delay from IRQA, IRQB, IRQD, NMI assertion to
general-purpose transfer output valid caused by first
interrupt instruction execution
4.25 × TC + 2.0
7.25 × TC + 2.0
10 × TC + 5.0
44.5 —
ns
74.5 —
ns
105.0 —
ns
19 Delay from address output valid caused by first interrupt 3.75 × TC + WS × TC – 10.94 —
instruction execute to interrupt request deassertion for level
sensitive fast interrupts 6, 7
—
ns
20 Delay from RD assertion to interrupt request deassertion 3.25 × TC + WS × TC – 10.94 —
for level sensitive fast interrupts6, 7
—
ns
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor
3-7
Share Link: 