Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 (continued)
No.
Characteristics
Expression2
Min Max Unit
21 Delay from WR assertion to interrupt request deassertion
ns
for level sensitive fast interrupts6, 7
• DRAM for all WS
• SRAM WS = 1
• SRAM WS = 2, 3
• SRAM WS ≥ 4
24 Duration for IRQA assertion to recover from Stop state
(WS + 3.5) × TC – 10.94
(WS + 3.5) × TC – 10.94
(WS + 3) × TC – 10.94
(WS + 2.5) × TC – 10.94
—
—
—
—
—
—
—
—
5.9
—
25 Delay from IRQA assertion to fetch of first instruction (when
exiting Stop)3, 8
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is enabled (OMR Bit 6 = 0)
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is not enabled (OMR Bit 6 = 1)
• PLL is active during Stop (PCTL Bit 17 = 1) (Implies No
Stop Delay)
PLC × ETC × PDF +
(128 K − PLC/2) × TC
PLC × ETC × PDF +
(23.75 ± 0.5) × TC
(8.25 ± 0.5) × TC
1.3 13.6 ms
232.5 12.3
ns
ms
77.5 87.5 ns
26 Duration of level sensitive IRQA assertion to ensure
interrupt service (when exiting Stop)3, 8
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is enabled (OMR Bit 6 = 0)
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is not enabled (OMR Bit 6 = 1)
• PLL is active during Stop (PCTL Bit 17 = 1) (implies no
Stop delay)
PLC × ETC × PDF +
(128 K − PLC/2) × TC
PLC × ETC × PDF +
(20.5 ± 0.5) × TC
5.5 × TC
13.6 — ms
12.3 — ms
55.0 —
ns
27 Interrupt Requests Rate
• ESAI, SCI
• DMA
• IRQ, NMI (edge trigger)
• IRQ, NMI (level trigger)
28 DMA Requests Rate
• Data read from ESAI, SCI
• Data write to ESAI, SCI
• IRQ, NMI (edge trigger)
12TC
8TC
8TC
12TC
6TC
7TC
3TC
— 120.0 ns
— 80.0 ns
— 80.0 ns
— 120.0 ns
— 60.0 ns
— 70.0 ns
— 30.0 ns
DSP56364 Technical Data, Rev. 4.1
3-8
Freescale Semiconductor