DSP56366 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56366

24-Bit Audio Digital Signal Processor

Freescale Semiconductor 

Table 3-4 Internal Clocks

Expression1, 2

Characteristics

Symbol

Min

Typ

Max

Internal clock cycle time with PLL

TC

—

2 × ETC

—

disabled

Instruction cycle time

ICYC

—

TC

—

1 DF = Division Factor

Ef = External frequency

ETC = External clock cycle

MF = Multiplication Factor

PDF = Predivision Factor

TC = internal clock cycle

2 See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL.

3.7 EXTERNAL CLOCK OPERATION

The DSP56366 system clock is an externally supplied square wave voltage source connected to EXTAL

(See Figure 3-1).

EXTAL

VILC ETH 2

ETL

3

4

ETC

Midpoint

Notes The midpoint is 0.5 (VIHC + VILC).

Figure 3-1 External Clock Timing

Table 3-5 Clock Operation

No.

Characteristics

1 Frequency of EXTAL (EXTAL Pin Frequency)

The rise and fall time of this external clock should be 3 ns maximum.

2 EXTAL input high1, 2

• With PLL disabled (46.7%–53.3% duty cycle3)

• With PLL enabled (42.5%–57.5% duty cycle3)

3 EXTAL input low1, 2

• With PLL disabled (46.7%–53.3% duty cycle3)

• With PLL enabled (42.5%–57.5% duty cycle3)

Symbol

Ef

ETH

ETL

VIHC

Min

0

3.89 ns

3.54 ns

3.89 ns

3.54 ns

Max

120.0

∞

157.0 μs

∞

157.0 μs

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-5

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