DSP56374UM View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56374UM Datasheet PDF : 64 Pages
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Signal Groupings
Table 11. Enhanced Serial Audio Interface_1 Signals (continued)
Signal Name Signal Type
SCKR_1 Input or output
State during
Reset
Signal Description
GPIO
disconnected
Receiver Serial Clock_1—SCKR_1 provides the receiver
serial bit clock for the ESAI_1. The SCKR_1 operates as a
clock input or output used by all the enabled receivers in the
asynchronous mode (SYN=0), or as serial flag 0 pin in the
synchronous mode (SYN=1).
PE0
Input, output, or
disconnected
When this pin is configured as serial flag pin, its direction is
determined by the RCKD bit in the RCCR_1 register. When
configured as the output flag OF0, this pin will reflect the
value of the OF0 bit in the SAICR_1 register, and the data
in the OF0 bit will show up at the pin synchronized to the
frame sync in normal mode or the slot in network mode.
When configured as the input flag IF0, the data value at the
pin will be stored in the IF0 bit in the SAISR_1 register,
synchronized by the frame sync in normal mode or the slot
in network mode.
Port E0—When the ESAI_1 is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
SCKT_1
PE3
Input or output
Input, output, or
disconnected
Internal Pull down resistor.
This input is 5 V tolerant
GPIO
disconnected
Transmitter Serial Clock_1—This signal provides the serial
bit rate clock for the ESAI_1. SCKT_1 is a clock input or
output used by all enabled transmitters and receivers in
synchronous mode, or by all enabled transmitters in
asynchronous mode.
Port E3—When the ESAI_1 is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
19
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