Timing Parameter Measured in Clock Cycle for Registered DIMM
Number of clock cycle
tCK
6ns
Parameter
Symbol min.
max.
Write to pre-charge command delay
(same bank)
tWPD
4 + BL/2
Read to pre-charge command delay
(same bank)
tRPD
BL/2
Write to read command delay
(to input all data)
tWRD
2 + BL/2
Burst stop command to write command delay
(CL = 3)
tBSTW
—
—
(CL = 3.5)
tBSTW 3
Burst stop command to DQ High-Z
(CL = 3)
tBSTZ
—
—
(CL = 3.5)
tBSTZ
3.5
3.5
Read command to write command delay
(to output all data)
tRWD
—
—
(CL = 3)
(CL = 3.5)
tRWD
3 + BL/2
Pre-charge command to High-Z
(CL = 3)
tHZP
—
—
(CL = 3.5)
tHZP
3.5
3.5
Write command to data in latency
tWCD
2
Write recovery
tWR
2
Register set command to active or register
set command
tMRD
2
Self refresh exit to non-read command
tSNR
12
Self refresh exit to read command
tSRD
200
Power down entry
tPDEN 1
1
Power down exit to command input
tPDEX 1
EBD10RD4ABFA
7.5ns
min.
max.
Unit
3 + BL/2
tCK
BL/2
tCK
2 + BL/2
tCK
2
tCK
3
tCK
3
3
tCK
3.5
3.5
tCK
2 + BL/2
tCK
3 + BL/2
tCK
3
3
tCK
3.5
3.5
tCK
2
2
tCK
1
tCK
2
tCK
10
tCK
200
tCK
1
1
tCK
1
tCK
Preliminary Data Sheet E0274E40 (Ver. 4.0)
14