EBE21AE8ACWA View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

Manufacturer

EBE21AE8ACWA

2GB Registered DDR2 SDRAM DIMM

Elpida Memory, Inc 

EBE21AE8ACWA

Parameter

Symbol Grade max. Unit

Test condition

Auto-refresh current IDD5

3876 mA

tCK = tCK (IDD);

Refresh command at every tRFC (IDD) interval;

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Self-refresh current

IDD6

297

mA

Self Refresh Mode;

CK and /CK at 0V;

CKE ≤ 0.2V;

Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING

Operating current

(Bank interleaving)

IDD7

4246 mA

all bank interleaving reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);

tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD),

tFAW = tFAW (IDD), tRCD = 1 × tCK (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are STABLE during DESELECTs;

Data pattern is same as IDD4W;

Notes: 1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate is specified by AC Input Test Condition.

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all

combinations of EMRS bits 10 and 11.

5. Definitions for IDD

L is defined as VIN ≤ VIL (AC) (max.)

H is defined as VIN ≥ VIH (AC) (min.)

STABLE is defined as inputs stable at an H or L level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as:

inputs changing between H and L every other clock cycle (once per two clocks) for address and control

signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals

not including masks or strobes.

6. Refer to AC Timing for IDD Test Conditions.

AC Timing for IDD Test Conditions

For purposes of IDD testing, the following parameters are to be utilized.

DDR2-667

Parameter

5-5-5

Unit

CL(IDD)

5

tCK

tRCD(IDD)

15

ns

tRC(IDD)

60

ns

tRRD(IDD)

7.5

ns

tFAW (IDD)

37.5

ns

tCK(IDD)

3

ns

tRAS(min.)(IDD)

45

ns

tRAS(max.)(IDD)

70000

ns

tRP(IDD)

15

ns

tRFC(IDD)

127.5

ns

Data Sheet E1396E10 (Ver. 1.0)

13

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