EBE21AE8ACWA View Datasheet(PDF) - Elpida Memory, Inc
Part Name
Description
Manufacturer
EBE21AE8ACWA Datasheet PDF : 27 Pages
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EBE21AE8ACWA
-6E
Speed bin
DDR2-667 (5-5-5)
Parameter
Active to auto-precharge delay
Active bank A to active bank B command period
Four active window period
Symbol
tRAP
tRRD
tFAW
min.
tRCD min.
7.5
37.5
max.
Unit
ns
ns
ns
Notes
/CAS to /CAS command delay
tCCD
2
nCK
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
tWR
tDAL
tWTR
15
WR + RU
(tRP/tCK(avg))
7.5
ns
nCK
1, 9
ns
14
Internal read to precharge command delay
tRTP
7.5
ns
Exit self-refresh to a non-read command
Exit self-refresh to a read command
tXSNR
tRFC + 10
ns
tXSRD
200
nCK
Exit precharge power down to any non-read command
Exit active power down to read command
Exit active power down to read command
(slow exit/low power mode)
CKE minimum pulse width (high and low pulse width)
tXP
tXARD
tXARDS
tCKE
2
2
7 − AL
3
nCK
nCK
3
nCK
2, 3
nCK
Output impedance test driver delay
tOIT
0
12
ns
MRS command to ODT update delay
tMOD
0
12
ns
Auto-refresh to active/auto-refresh command time
tRFC
127.5
ns
Average periodic refresh interval
(0°C ≤ TC ≤ +85°C)
tREFI
7.8
µs
(+85°C < TC ≤ +95°C)
tREFI
3.9
µs
Minimum time clocks remains ON after CKE
asynchronously drops low
tDELAY
tIS + tCK(avg) + tIH
ns
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the device under test.
DQS
CK
/DQS
/CK
tDS tDH
tDS tDH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
tIS
tIH
tIS
tIH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Data Sheet E1396E10 (Ver. 1.0)
17
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