H5PS1G43EFR View Datasheet(PDF) - Hynix Semiconductor

Part Name

Description

Manufacturer

H5PS1G43EFR

1Gb DDR2 SDRAM

Hynix Semiconductor 

H5PS1G43EFR

H5PS1G83EFR

H5PS1G63EFR

Note :

1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V (exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed

grade)

2. IDD specifications are tested after the device is properly initialized

3. Input slew rate is specified by AC Parametric Test Condition

4. IDD parameters are specified with ODT disabled.

5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met

with all combinations of EMR bits 10 and 11.

6. For DDR2-667/800 testing, tCK in the COnditions should be interpreted as tCK (avg).

7. Definitions for IDD

LOW is defined as Vin ≤ VILAC (max)

HIGH is defined as Vin ≥ VIHAC (min)

STABLE is defined as inputs stable at a HIGH or LOW level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)

for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per

clock) for DQ signals not including masks or strobes.

Rev. 0.4 / Nov 2008

18

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