HT66F016/HT66F017/HT68F016/HT68F017
A.C. Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
VDD
Conditions
¾ 2.2V~5.5V
Min.
DC
fCPU
Operating Clock
2.7V~5.5V
DC
¾
4.5V~5.5V
DC
2.2V~5.5V
0.4
fSYS
System Clock (HXT)
¾ 2.7V~5.5V
0.4
4.5V~5.5V
0.4
fHIRC
System Clock (HIRC)
3.0V~
5.5V
Ta= -40°C~85°C
4.5V~
5.5V
Ta= -40°C~85°C
-6%
-2%
fLIRC
tINT
tLVR
tLVD
tLVDS
tBGS
tTIMER
tSRESET
tRSTD
System Clock (LIRC)
Interrupt Pulse Width
Low Voltage Width to Reset
Low Voltage Width to Interrupt
LVDO stable time
VBG Turn on Stable Time
TCKn Input Pulse Width
Software Reset Width to Reset
System Reset Delay Time
(Power on Reset)
System Reset Delay Time (Any
Reset except Power on Reset)
5V Ta=25°C
-10%
¾
¾
10
¾
¾
120
¾
¾
20
¾ For all VLVD, LVR disable 200
¾
¾
200
¾
¾
0.3
¾
¾
45
¾
¾
25
¾
¾
8.3
System Start-up Timer Period
fSYS=HXT OSC
128
(Wake-up from HALT, fSYS off at ¾ fSYS=HIRC OSC
16
HALT State)
tSST
fSYS=LIRC OSC
2
System Start-up Timer Period
(Wake-up from HALT, fSYS on at ¾
¾
2
HALT State)
tEERD
EEPROM Read Time
¾
¾
¾
tEEWR
EEPROM Write Time
¾
¾
¾
Typ.
¾
¾
¾
¾
¾
¾
8
8
32
¾
240
45
¾
¾
¾
90
50
16.7
¾
¾
¾
¾
2
2
Max.
8
12
20
8
12
20
+6%
+2%
+10%
¾
480
90
¾
¾
¾
120
100
33.3
¾
¾
¾
¾
4
4
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
ms
ms
ms
ms
ms
ms
ms
ms
ms
tSYS
tSYS
tSYS
ms
Note:
1. tSYS=1/fSYS
2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should be
connected between VDD and VSS and located as close to the device as possible.
Rev. 1.00
14
May 14, 2012