HT82V46
ADCK
16.5 ADCK
CDS2
Analog
Input
(R, G, B)
OD[7:0]
DLY[1:0] = 00
B R R GGB B R R GGB B R R GGB B R R GGB B RR GGB B RR GGB
LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB
DLY[1:0] = 01
R R GGB B
HB LB HB LB HB LB
DLY[1:0] = 10
R R GGB B
HB LB HB LB HB LB
HB : High Byte; LB : Low Byte
DLY[1:0] = 11
R R GGB B
HB LB HB LB HB LB
Figure 6 MODE1 : 3-channel Pixel-by-Pixel
ADCK
16.5 ADCK
CDS2
Analog
Input
(R, G, B)
OD[7:0]
X HB LB X X X X HB LB X X X X HB LB X X X X HB LB X X X X HB LB X X X X HB LB X X X
DLY[1:0] = 00
DLY[1:0] = 01
HB LB
DLY[1:0] = 10
HB LB
DLY[1:0] = 11
HB : High Byte; LB : Low Byte; X : Invalid Data
Figure 7 MODE2 : 1-channel Line-by-Line
HB LB
Rev. 1.10
11
November 24, 2011