IDTCV107E View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDTCV107E Datasheet PDF : 21 Pages
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IDTCV107E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
BYTE 32: WD SOFT RESET TIMER
WD Soft Alarm timer has to be shorter than WD Hard Alarm timer. WDE and WD Soft Alarm bits, Byte 33 bit 7 and bit 5, have to be enabled for this Soft Alarm
function.
Bit
Output(s) Affected
Description/Function
0
1
Type
Power On
7
CPU WD Hard Alarm
0 = frequency select controlled by Byte 25 bit 7 HW/SMBus WDBS
RW
0
safe frequency mode select
1 = CPU frequency specified
WDCFS
by WDBS[2:0] WDCFS[2:0]
6
WDCFS2
CPU WD time out safe frequency select(1)
RW
0
5
WDCFS1
RW
0
4
WDCFS0
RW
0
3
WD soft alarm timer 3
Specify WD Soft Alarm Time Out time
RW
0
2
WD soft alarm timer 2
Time Out time = WD Soft Alarm Timer[3:0]*290ms
RW
0
1
WD soft alarm timer 1
Default is 580ms.
RW
1
0
WD soft alarm timer 0
RW
0
NOTE:
1. See SW FREQUENCY SELECTION table.
BYTE 33: WD CONTROL
Bit
Output(s) Affected
Description/Function
0
1
Type
7
WDE
Watchdog enable
Disable Enable
RW
6
WD FS relatch
Relatch HW FS2, 1, 0
Disable Enable
RW
in event of WD Hard Alarm time out
5
WD Soft Alarm enable
WD Soft Alarm enable
Disable Enable
RW
4
AGP/PCI WD Hard Alarm
In event of WD Hard Alarm time out
HW/SMBus WDAFS
RW
time out safe frequency mode select 0 = AGP/PCI frequency controlled by Byte 30 bit 6
1 = AGP/PCI frequency specified by WDAFS[2:0]
3
SRC SMC 2
SRC SSC magnitude control(1)
2
SRC SMC 1
SRC SSC magnitude control(1)
1
SRC SMC 0
SRC SSC magnitude control(1)
0
Reserve
NOTE:
1. See SMC table.
Power On
0
0
0
0
1
0
1
0
BYTE 34
Bit
Output(s) Affected
Description/Function
0
1
Type
7
SW 24_48MHz control override 0 = controlled by hardware, 1 = controlled by bit 6 HW control controlledby RW
bit 6
6
24_48MHz select
48MHz 24MHz
RW
5
Reserve
RW
4
3
2
1
0
Power On
0
0
0
0
0
13
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