IP1000ALF-DS-R01 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

IP1000ALF-DS-R01

Gigabit Ethernet NIC Single Chip

Unspecified 

IP1000A LF

Preliminary Data Sheet

A common use of interrupts during transmit DMA operation is to determine which TFDs have been

successfully transmitted so the host system can free the memory occupied by old TFDs. Interrupts

however usually incur a significant cost in terms of host system performance, requiring a large

percentage of processor time to service. While interrupts are expensive, memory is usually abundant,

therefore a trade off which minimizes interrupts in exchange for more memory usage is desirable.

2.2.4.2 Interrupt-Less Transmit DMA

IP1000A LF's transmit DMA can operate without generating host system processor interrupts. In this

mode of operation, the host system does not set the TxIndicate or TxDMAIndicate bits in the TFC0 field

of any TFDs used to transfer Ethernet frames from system memory. Thus, an interrupt is not issued by

the IP1000A LF to indicate successful DMA transfer or successful transmission of each Ethernet frame.

An interrupt will only be issued by the IP1000A LF in the event of a transmit error, but this case should be

rare.

Without the use of interrupts, the IP1000A LF provides another mechanism for the host system to

determine which Ethernet frames have been successfully transmitted. This mechanism allows the host

system to free memory locations holding old TFD lists. This “interrupt-less” mechanism involves using

the TxFrameId field of the TxStatus register. The TxFrameId field of the TxStatus register indicates the

last Ethernet frame which was successfully transmitted. Using this information, the host system can infer

successful transmission of all Ethernet frames up to the frame indicated by the TxFrameId field of the

TxStatus register. Thus, the host system decides when to poll the TxFrameId field of the TxStatus

register (for example, when the amount of memory occupied by old TFD lists becomes excessive) and

avoid generation of processor intensive interrupts by the IP1000A LF.

2.2.4.3 Receive DMA Interrupts

Interrupts can be generated by the IP1000A LF based on a number of events related to receive DMA

operation:

RxDMAComplete interrupt is issued after successful transfer of one or more Ethernet frames (based

on the interrupt coalescing configuration) from the IP1000A LF to the host system memory. Interrupt

coalescing should be used in conjunction with the RxDMAComplete interrupt given the frequency of

frame receipts in a Gigabit Ethernet network.

RxDMAPriority interrupt is issued if a received Ethernet frame contains a Tag Control Information

field with priority greater than or equal to the priority set in the RxDMAIntCtrl register.

RFDListEnd interrupt is issued if the end of the RFD list is reached (indicated by an RFDNextPtr field

with a value of 0x0000000000), or a RFD with the RFDDone bit of the RFS field with a value of logic

1 is encountered.

2.2.4.4 Receive DMA Interrupt Coalescing

A common use of interrupts during receive DMA operation is to indicate when new Ethernet frames have

been transferred to host system memory. Interrupts however usually incur a significant cost in terms of

host system performance, requiring a large percentage of processor time to service. One way to

minimize the number of interrupts issued by the IP1000A LF related to receive DMA operation is to issue

a single interrupt to indicate multiple Ethernet frames have been received. While minimizing interrupts

can improve host system performance, it can also require more host system memory usage, and

increase network latency. Therefore, a balance between interrupt frequency and network latency must

be reached by the host system to optimize performance. Note: interrupt coalescing only applies to the

nominal TFD list. Priority TFD lists do not utilize interrupt coalescing.

2.2.5 ACPI

The IP1000A LF supports operating system directed power management according to the ACPI

specification. Power management registers in the PCI configuration space, as defined by the PCI Bus

Power Management Interface specification, Revision 1.1

Copyright © 2005, IC Plus Corp.

15/75

July 5, 2005

IP1000A LF-DS-R08

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