IS42S16800E View Datasheet(PDF) - Integrated Silicon Solution
Part Name
Description
Manufacturer
IS42S16800E Datasheet PDF : 61 Pages
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IS42S81600E, IS42S16800E
AC ELECTRICAL CHARACTERISTICS (1,2,3)
-5 -6 -7 -75E
Symbol Parameter
tck3
Clock Cycle Time
tck2
CAS Latency = 3
CAS Latency = 2
tac3
Access Time From CLK
tac2
CAS Latency = 3
CAS Latency = 2
Min. Max.
5—
10 —
—5
— 6.5
Min. Max.
6—
10 —
— 5.4
— 6.5
Min. Max.
7—
10 —
— 5.4
— 6.5
Min. Max. Units
— — ns
7.5 — ns
— — ns
— 5.5 ns
tchi
CLK HIGH Level Width
2—
2.5 —
2.5 —
2.5 — ns
tcl
CLK LOW Level Width
toh3
Output Data Hold Time
toh2
CAS Latency = 3
CAS Latency = 2
2—
2.5 —
2.5 —
2.5 —
2.7 —
2.7 —
2.5 —
2.7 —
2.7 —
2.5 — ns
2.7 — ns
2.7 — ns
tlz
Output LOW Impedance Time
0—
0—
0—
0 — ns
thz
Output HIGH Impedance Time
2.5 5
2.7 5.4
2.7 5.4
2.7 5.4 ns
tds
Input Data Setup Time(2) 1.5 —
1.5 —
1.5 —
1.5 — ns
tdh
Input Data Hold Time(2)
0.8 —
0.8 —
0.8 —
0.8 — ns
tas
Address Setup Time(2) 1.5 —
1.5 —
1.5 —
1.5 — ns
tah
Address Hold Time(2)
0.8 —
0.8 —
0.8 —
0.8 — ns
tcks
CKE Setup Time(2) 1.5 —
1.5 —
1.5 —
1.5 — ns
tckh
CKE Hold Time(2)
0.8 —
tcs
Command Setup Time (CS, RAS, CAS, WE, DQM)(2) 1.5 —
tch
Command Hold Time (CS, RAS, CAS, WE, DQM)(2) 0.8 —
0.8 —
1.5 —
0.8 —
0.8 —
1.5 —
0.8 —
0.8 — ns
1.5 — ns
0.8 — ns
trc
Command Period (REF to REF / ACT to ACT)
55 —
60 —
67.5 —
67.5 — ns
tras
Command Period (ACT to PRE)
38 100K
42 100K
45 100K
45 100K ns
trp
Command Period (PRE to ACT)
15 —
18 —
20 —
15 — ns
trcd Active Command To Read / Write Command Delay Time 15 —
18 —
20 —
15 — ns
trrd
Command Period (ACT [0] to ACT[1])
10 —
12 —
14 —
15 — ns
tdpl
Input Data To Precharge
Command Delay time
10 —
12 —
14 —
15 — ns
tdal
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
25 —
30 —
35 —
30 — ns
tmrd Mode Register Program Time
10 —
12 —
15 —
15 — ns
tdde
Power Down Exit Setup Time
5—
6.0 —
7.0 —
7.5 — ns
txsr Exit Self-Refresh to Active Time
60 —
67 —
70 —
70 — ns
tt
Transition Time
0.3 1.2
0.3 1.2
0.3 1.2
0.3 1.2 ns
tref
Refresh Cycle Time (4096)
— 64
— 64
— 64
— 64 ms
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with tt = 1 ns. If clock rising time is longer than 1ns, (tr /2 - 0.5) ns should be added to the parameter.
3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between Vih(min.) and Vil (max).
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. B
05/27/09
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