LH28F008SCT-12 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F008SCT-12

Flash Memory 8M (1M ×8)

Sharp Electronics 

LHF08CH3

13

When the block erase is complete, status register bit

SR.5 should be checked. If a block erase error is

detected, the status register should be cleared before

system software attempts corrective actions. The CUI

remains in read status register mode until a new

command is issued.

This two-step command sequence of set-up followed

by execution ensures that block contents are not

accidentally erased. An invalid Block Erase command

sequence will result in both status register bits SR.4

and SR.5 being set to “1 ‘I. Also, reliable block erasure

can only occur when Vcc=Vcc2,s and Vpp=VppH1,2,3.

In the absence of this high voltage, block contents

are protected against erasure. If block erase is

attempted while V,,IV,,,k,

SR.3 and SR.5 will be

set to “1 ‘I. Successful block erase requires that the

corresponding block lock-bit be cleared or, if set, that

RP#=V,,. If block erase is attempted when the

corresponding block lock-bit is set and RP#=V,,,

SR.l and SR.5 will be set to “1”. Block erase

operations with V,,<RP#CV,~ produce spurious

,esults and should not be attempted.

4.6 Byte Write Command

3yte write is executed by a two-cycle command

sequence. Byte write setup (standard 40H or

alternate 10H) is written, followed by a second write

:hat specifies the address and data (latched on the

ising edge of WE#). The WSM then takes over,

:ontrolling the byte write and write verify algorithms

nternally. After the byte write sequence is written, the

device automatically outputs status register data

Nhen read (see Figure 6). The CPU can detect the

:ompletion of the byte write event by analyzing the

qY/BY# pin or status register bit SR.7.

Nhen byte write is complete, status register bit SR.4

;hould be checked. If byte write error is detected, the

;tatus register should be cleared. The internal WSM

verify only detects errors for “1”s that do not

;uccessfully write to “0%. The CUI remains in read

;tatus register mode until it receives another

:ommand.

qeliable byte writes can only occur when Vcc=Vcc2/s

Ind VPP=VPPH1/2/3-

In the absence of this high

loltage, memory contents are protected against byte

vrites. If byte write is attempted while Vpp~Vpp,,,

status register bits SR.3 and SR.4 will be set to “1”.

juccessful byte write requires that the corresponding

block lock-bit be cleared or, if set, that RP#=VHH. I

byte write is attempted when the corresponding bloc1

lock-bit is set and RP#=VrH, SR.l and SR.4 will bc

set to “1 ‘I. Byte write operations with VrH<RP#<Vr+

produce spurious results and should not bt

attempted.

4.7 Block Erase Suspend Command

The Block Erase Suspend command allow:

block-erase interruption to read or byte-write data ir

another block of memory. Once the block-erase

process starts, writing the Block Erase Suspenc

command requests that the WSM suspend the bloc+

erase sequence at a predetermined point in the

algorithm. The device outputs status register dat:

when read after the Block Erase Suspend commanc

is written. Polling status register bits SR.7 and SR.E

can determine when the block erase operation ha:

been suspended (both will be set to “1”). RY/BY# wil

also transition to VOH. Specification twHr$+ defines

the block erase suspend latency.

At this point, a Read Array command can be writter

to read data from blocks other than that which is

suspended. A Byte Write command sequence car-

also be issued during erase suspend to program data

in other blocks. Using the Byte Write Suspenc

command (see Section 4.8), a byte write operation

can also be suspended. During a byte write operation

with block erase suspended, status register bit SR.7

will return to “0” and the RY/BY# output will transition

to V,,. However, SR.6 will remain “1” to indicate

block erase suspend status.

The only other valid commands while block erase is

suspended are Read Status Register and Block

Erase Resume. After a Block Erase Resume

command is written to the flash memory, the WSM

will continue the block erase process. Status register

bits SR.6 and SR.7 will automatically clear and

RY/BY# will return to V,,. After the Erase Resume

command is written, the device automatically outputs

status register data when read (see Figure 7). VP,

must remain at VppHr,2/3 (the same Vpp level used

for block erase) while block erase is suspended. RP#

must also remain at VrH or VHH (the same RP# level

used for block erase). Block erase cannot resume

until byte write operations initiated during block erase

suspend have completed.

Rev. 1.0

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