LH28F008SCT-12 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
Manufacturer
LH28F008SCT-12 Datasheet PDF : 49 Pages
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SHARP
LHF08CH3
14
4.8 Byte Write Suspend Command
The Byte Write Suspend command allows byte write
interruption to read data in other flash memory
locations. Once the byte write process starts, writing
the Byte Write Suspend command requests that the
WSM suspend the byte write sequence at a
predetermined point in the algorithm. The device
continues to output status register data when read
after the Byte Write Suspend command is written.
Polling status register bits 33.7 and SR.2 can
determine when the byte write operation has been
suspended (both will be set to “1”). RY/BY# will also
transition to V,,. Specification t,,,,, defines the
byte write suspend latency.
At this point, a Read Array command can be written
to read data from locations other than that which is
suspended. The only other valid commands while
Dyte write is suspended are Read Status Register
and Byte Write Resume. After Byte Write Resume
:ommand is written to the flash memory, the WSM
NilI continue the byte write process. Status register
3ts SR.2 and SR.7 will automatically clear and
:;;ize wi;o;;;;dto
V,,. 4fter thethydrv;;z
IS wntten,
automatically outputs status register data when read
:see Figure 8). V,, must remain at V,,,,,,,, (the
same V,, level used for byte write) while in byte write
suspend mode. RP# must also remain at V,, or V,,
:the same RP# level used for byte write).
1.9 Set Block and Master Lock-Bit
Commands
4 flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a
naster lock-bit. The block lock-bits gate program and
erase operations while the master lock-bit gates
Ilock-lock bit modification. With the master lock-bit
lot set, individual block lock-bits can be set using the
jet Block Lock-Bit command. The Set Master
.ock-Bit command, in conjunction with RP#=V,,,
bets the master lock-bit. After the master lock-bit is
;et, subsequent setting of block lock-bits requires
joth the Set Block Lock-Bit command and V,, on
the RP# pin. See Table 6 for a summary of hardwan
and software write protection options.
Set block lock-bit and master lock-bit are executed b!
a two-cycle command sequence. The set block o
master lock-bit setup along with appropriate block o
device address is written followed by either the se
block lock-bit confirm (and an address within tht
block to be locked) or the set master lock-bit confirn
(and any device address). The WSM then control:
the set lock-bit algorithm. After the sequence i:
written, the device automatically outputs statu:
register data when read (see Figure 9). The CPU car
detect the completion of the set lock-bit event b\
analyzing the RY/BY# pin output or status register bi
SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error iz
detected, the status register should be cleared. The
CUI will remain in read status register mode until i
new command is issued.
This two-step sequence of set-up followed bb
execution ensures that lock-bits are not accidentall]
set. An invalid Set Block or Master Lock-Bil
command will result in status register bits SR.4 ant
SR.5 being set to “1 ‘I. Also, reliable operations OCCUI
only when Vcc=Vcc2,3 and VPP=VPPH,,2/3. In the
absence of this high voltage, lock-bit contents are
protected against alteration.
A successful set block lock-bit operation requires thai
the master lock-bit be cleared or, if the master
lock-bit is set, that RP#=V,,. If it is attempted with
the master lock-bit set and RP#=V,,, SR.l and SR.4
will be set to “1” and the operation will fail. Set block
lock-bit operations while VIHcRP#cV,,
produce
spurious results and should not be attempted. A
successful set master lock-bit operation requires that
RP#=V,,. If it is attempted with RP#=V,,, SR.l and
SR.4 will be set to “1” and the operation will fail. Set
master lock-bit operations with V,,cRP#<V,,
produce spurious results and should not be
attempted.
Rev. 1.0
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