LH79524 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

LH79524

System-on-Chip

NXP Semiconductors. 

LH79524/LH79525

NXP Semiconductors

System-on-Chip

PIN NO. SIGNAL NAME

163 PH7/ETHERTX3

4 PI0/ETHERMDC

2 PI1/ETHERMDIO

1 PI2/ETHERCOL

176 PI3/ETHERCRS

175 PI4/ETHERRXER

174 PI5/ETHERRX0

173 PI6/ETHERRX1

172 PI7/ETHERRX2

24 nRESETIN

22 nRESETOUT

127 XTALIN

128 XTALOUT

125 XTAL32IN

126 XTAL32OUT

23 CLKOUT

8 nTRST

50 TMS

51 TCK

46 TDI

45 TDO

47 TEST1

48 TEST2

9 LINREGEN

6, 66,

107, 150

VDDC

7, 64,

105,148

VSSC

3, 26, 33,

57, 75,

86, 101, VDD

129, 135,

144, 160

5, 27, 49,

68, 81,

92, 108, VSS

132, 140,

152, 168

10 VDDA0

122 VDDA1

123 VDDA2

21 VSSA0

121 VSSA1

124 VSSA2

Table 5. LH79525 Pin Descriptions (Cont’d)

TYPE

DESCRIPTION

I/O General Purpose I/O Signals — Port H7; multiplexed with Ethernet Transmit Channel 3

I/O

General Purpose I/O Signals — Port I0; multiplexed with Ethernet Management

Data Clock

I/O General Purpose I/O Signals — Port I1; multiplexed with Ethernet Management Data I/O

I/O General Purpose I/O Signals — Port I2; multiplexed with Ethernet Collision Detect

I/O General Purpose I/O Signals — Port I3; multiplexed with Ethernet Carrier Sense

I/O General Purpose I/O Signals — Port I4; multiplexed with Ethernet Receive Error

I/O General Purpose I/O Signals — Port I5; multiplexed with Ethernet Receive Channel 0

I/O General Purpose I/O Signals — Port I6; multiplexed with Ethernet Receive Channel 1

I/O General Purpose I/O Signals — Port I7; multiplexed with Ethernet Receive Channel 2

I Reset Input

O Reset Output

I Crystal Input, or external clock input

O Crystal Output

I 32.768 kHz Crystal Oscillator Input, or external clock input,

O 32.768 kHz Crystal Oscillator Output

O Clock Out (selectable from the internal bus clock or 32.768 MHz)

I JTAG Test Reset Input

I JTAG Test Mode Select Input

I JTAG Test Clock Input

I JTAG Test Serial Data Input

O JTAG Test Data Serial Output

I Tie HIGH for Normal Operation; pull LOW to enable embedded ICE Debugging

I Tie HIGH for Normal Operation; pull HIGH to enable embedded ICE Debugging

I Linear Regulator Enable (Requires pull-up. See User’s Guide)

Power Core Power Supply

Ground Core GND

Power Input/Output Power Supply

Ground Input/Output GND

Power Analog Power Supply for Analog-to-Digital Converter

Power Analog Power Supply for the USB PLL

Power Analog Power Supply for System PLL

Ground Analog GND for Analog-to-Digital Converter

Ground Analog GND for the USB PLL

Ground Analog GND for System PLL

Table 6. LH79525 Numerical Pin List

PIN FUNCTION

NO. AT RESET

MULTIPLEXED

FUNCTION(S)

1

PI2

ETHERCOL

OUTPUT

DRIVE

NOTES

8 mA

1

Table 6. LH79525 Numerical Pin List (Cont’d)

PIN FUNCTION

NO. AT RESET

MULTIPLEXED

FUNCTION(S)

2

PI1

ETHERMDIO

OUTPUT

DRIVE

NOTES

8 mA

2

16

Rev. 02 — 17 March 2009

Product data sheet

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