LP1071 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

LP1071

802.11a/b/g Baseband System Solution

Freescale Semiconductor 

LP1071 Interfaces

Table 8. SDIO Function 1 Registers (continued)

Bit

Name

Description

ARM

Access

SDIO Host Mailbox Semaphore 2 Register (offset 0x001E)

1:0

Sdio_mbxp_2_sema

2 bit semaphore register to control whether the

RW

host or the device has access to the shared

mailbox ram 2. The host should write a “01” to this

register to request the shared ram 2. After writing

“01” the host should read this register. If the value

is “01” then the host owns access to the mailbox.

If the value read is “11” then the device owns

access to the mailbox. When the host is done

utilizing the mailbox then it should release

ownership of the mailbox by writing “00” to this

register.

7:2

Reserved

—

—

992 byte Mailbox RAM 1 (offset 0x200F to 0x23FF)

7:0

Mbox_rdata_1[15:0]

Shared SDIO Mailbox. Both the ARM and Host

RW

can use the mailbox for message exchange

between the SDIO device and the SDIO Host.

Prior to accessing the SDIO Mailbox the Host

should request and be granted the mailbox via the

mailbox semaphore 1 register described above.

Once the Host has been granted access to the

mailbox it may read/write the mailbox however it

likes. If the Host has not been granted access to

the mailbox it will not be able to read or write the

mailbox. Once the Host is finished with the

mailbox it should release control of the mailbox as

described in the mailbox semaphore 1 register.

1 Kbyte Mailbox RAM 2 (offset 0x2400 to 0x27FF)

7:0

Mbox_rdata_2[15:0]

Shared SDIO Mailbox. Both the ARM and Host

RW

can use the mailbox for message exchange

between the SDIO device and the SDIO Host.

Prior to accessing the SDIO Mailbox the Host

should request and be granted the mailbox via the

mailbox semaphore 2 register described above.

Once the Host has been granted access to the

mailbox it may read/write the mailbox however it

likes. If the Host has not been granted access to

the mailbox it will not be able to read or write the

mailbox. Once the Host is finished with the

mailbox it should release control of the mailbox as

described in the mailbox semaphore 2 register.

HOST

Access

RW

—

RW

RW

Reset

0’s

—

—

—

LP1071 Advance Information, Rev. 0.5

14

Freescale Semiconductor

PRELIMINARY

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