LPC47M172-NR View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

LPC47M172-NR

Advanced I/O Controller with Motherboard GLUE Logic

SMSC -> Microchip 

PIN#

16

NAME

(NOTE 1)

nSTEP

17

nDIR

18

nDS0

19

nMTR0

20

nINDEX

21

DRVDEN1

22

DRVDEN0

23

nDCD1

24

nDSR1

25

RXD1

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

DESCRIPTION

BUFFER

NAME

(NOTE 2)

Step Pulse Output. This active low high O12

current driver issues a low pulse for each

track-to-track movement of the head.

Can be configured as an Open-Drain

Output.

Step Direction Output. This high current O12

low active output determines the direction

of the head movement. A logic “1” on this

pin means outward motion, while a logic

“0” means inward motion. Can be

configured as an Open-Drain Output.

Drive Select 0 Output. Can be configured O12

as an Open-Drain Output.

Motor On 0 Output. Can be configured as O12

an Open-Drain Output.

This active low Schmitt Trigger input

IS

senses from the disk drive that the head

is positioned over the beginning of a

track, as marked by an index hole.

Drive Density Select 1 Output. Indicates O12

the drive and media selected. Can be

configured as Open-Drain Output.

Drive Density Select 0 Output. Indicates O12

the drive and media selected. Can be

configured as Open-Drain Output.

SERIAL PORT 1 INTERFACE (8)

Active low Data Carrier Detect input for

I

the serial port. Handshake signal that

notifies the UART that carrier signal is

detected by the modem. The CPU can

monitor the status of nDCD signal by

reading bit 7 of Modem Status Register

(MSR). A nDCD signal state change from

low to high after the last MSR read will set

MSR bit 3 to a 1. If bit 3 of Interrupt

Enable Register is set, the interrupt is

generated when nDCD changes state.

Note: Bit 7 of MSR is the complement of

nDCD.

Active low Data Set Ready input for the I

serial port. Handshake signal that notifies

the UART that the modem is ready to

establish the communication link. The

CPU can monitor the status of nDSR

signal by reading bit 5 of Modem Status

Register (MSR). A nDSR signal state

change from low to high after the last

MSR read will set MSR bit 1 to a 1. If bit

3 of Interrupt Enable Register is set, the

interrupt is generated when nDSR

changes state.

Note: Bit 5 of MSR is the complement of

nDSR.

Receiver serial data input.

IS

PWR

WELL

(NOTE 3)

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

NOTES

SMSC/Non-SMSC Register Sets (Rev. 02-27-04)

Page 17

DATASHEET

SMSC LPC47M172

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