LPC47M172-NR View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

LPC47M172-NR

Advanced I/O Controller with Motherboard GLUE Logic

SMSC -> Microchip 

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

PIN#

26

NAME

(NOTE 1)

nRTS1

27

TXD1

28

nCTS1

30

nDTR1

(XOR)

32

nRI1

118 nRI2

119 RXD2

120 TXD2

DESCRIPTION

BUFFER

NAME

(NOTE 2)

Active low Request to Send output for the O8

Serial Port. Handshake output signal

notifies modem that the UART is ready to

transmit data. This signal can be

programmed by writing to bit 1 of the

Modem Control Register (MCR). The

hardware reset will reset the nRTS signal

to inactive mode (high). nRTS is forced

inactive during loop mode operation.

Transmit serial data output.

O12

Active low Clear to Send input for the

I

serial port. Handshake signal that notifies

the UART that the modem is ready to

receive data. The CPU can monitor the

status of nCTS signal by reading bit 4 of

Modem Status Register (MSR). A nCTS

signal state change from low to high after

the last MSR read will set MSR bit 0 to a

1. If bit 3 of the Interrupt Enable Register

is set, the interrupt is generated when

nCTS changes state. The nCTS signal

has no effect on the transmitter.

Note: Bit 4 of MSR is the complement of

nCTS.

Active low Data Terminal Ready output

O8

for the serial port. Handshake output

signal notifies modem that the UART is

ready to establish data communication

link. This signal can be programmed by

writing to bit 0 of Modem Control Register

(MCR). The hardware reset will reset the

nDTR signal to inactive mode (high).

nDTR is forced inactive during loop mode

operation.

XOR Chain Output.

Active low Ring Indicator input for the

I

serial port. Handshake signal that notifies

the UART that the telephone ring signal is

detected by the modem. The CPU can

monitor the status of nRI signal by

reading bit 6 of Modem Status Register

(MSR). A nRI signal state change from

low to high after the last MSR read will set

MSR bit 2 to a 1. If bit 3 of Interrupt

Enable Register is set, the interrupt is

generated when nRI changes state.

Note: Bit 6 of MSR is the complement of

nRI.

SERIAL PORT 2 INTERFACE (8)

Active low Ring Indicator input for serial IPD

port 2. See description for nRI1.

Receiver serial data input.

ISPD_400

Transmit serial data output.

O12

PWR

WELL

(NOTE 3)

VCC

NOTES

VCC

VCC

VCC

VTR

6

VTR

VCC

VCC

6, 10

SMSC/Non-SMSC Register Sets (Rev. 02-27-04)

Page 18

DATASHEET

SMSC LPC47M172

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