M470L3223DT0 View Datasheet(PDF) - Samsung
Part Name
Description
Manufacturer
M470L3223DT0 Datasheet PDF : 16 Pages
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M470L3223DT0
Parameter
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
DQ & DM input pulse width
Power down exit time
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
64Mb, 128Mb
256Mb
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Autoprecharge write recovery +
Precharge time
-TCA2(DDR266A)
Symbol
Min
Max
tMRD
15
tDS
0.5
tDH
0.5
tDIPW 1.75
tPDEX
7.5
tXSNR
75
tXSRD
200
tREFI
15.6
7.8
tQH
tHP
-tQHS
-
tHP
tCLmin
or tCHmin
-
tQHS
0.75
tWPST
0.4
0.6
tDAL
(tWR/tCK)
+
(tRP/tCK)
-TCB0(DDR266B)
Min
Max
15
0.5
0.5
1.75
7.5
75
200
15.6
7.8
tHP
-tQHS
-
tCLmin
or tCHmin
-
0.75
0.4
0.6
(tWR/tCK)
+
(tRP/tCK)
-TCA0 (DDR200)
Min
Max
16
0.6
0.6
2
10
80
200
15.6
7.8
tHP
-tQHS
-
tCLmin
or tCHmin
-
0.8
0.4
0.6
(tWR/tCK)
+
(tRP/tCK)
Unit Note
ns
ns 7,8,9
ns 7,8,9
ns
ns
ns 4
tCK
us 1
us 1
ns 5
ns
ns
tCK 3
tCK 11
1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period
jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
Rev. 0.0 Dec. 2001
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