AS4C1M16F5 View Datasheet(PDF) - Alliance Semiconductor

Part Name

Description

Manufacturer

AS4C1M16F5

5V 1M×16 CMOS DRAM (fast-page mode)

Alliance Semiconductor 

AS4C1M16F5

®

Functional description

The AS4C1M16F5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as

1,048,576 words × 16 bits. The AS4C1M16F5 is fabricated using advanced CMOS technology and innovative design

techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The

Alliance 16Mb DRAM family is optimized for use as main memory in personal and portable PCs, workstations, and multimedia

and router switch applications.

The AS4C1M16F5 features high speed page mode operation where read and write operations within a single row (or page)

can be executed at very high speed (15 ns from XCAS)by toggling column addresses within that row. Row and column

addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs respectively. Also, RAS is used

to make the column address latch transparent, enabling application of column addresses prior to xCAS assertion. The

AS4C1M16F5 provides dual UCAS and LCAS for independent byte control of read and write access.

Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using:

• RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence.

• Hidden refresh: xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data.

• CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally.

Outputs are high-impedence (OE and WE are don't care).

• Normal read or write cycles refresh the row being accessed.

The AS4C1M16F5 is available in the standard 42-pin plastic SOJ and the 44/50-pin TSOP II packages, respectively. It operates

with a single power supply of 5V ± 0.5V. The device provides TTL compatible inputs and outputs.

Logic block diagram

VCC

GND

RAS

RAS clock

generator

A0

A1

A2

A3

UCAS

CAS clock

generator

A4

A5

LCAS

A6

A7

A8

WE clock

A9

WE

generator

Column decoder

Sense amp

Data

DQ

buffers

DQ1 to DQ16

1024 × 1024 × 16

Array

(16,777,216)

OE

Substrate bias

generator

Recommended operating conditions

Parameter

Symbol

Min

Supply voltage

AS4C1M16F5

VCC

4.5

GND

0.0

Input voltage

AS4C1M16F5

VIH

2.4

VIL

–0.5†

Commercial

0

Ambient operating temperature

Industrial

TA

-40

†VIL min -3.0V for pulse widths less than 5 ns.

Recommended operating conditions apply throughout this document unlesss otherwise specified.

Nominal

5.0

0.0

–

–

–

–

Max Unit

5.5 V

0.0 V

VCC

V

0.8 V

70

°C

85

4/11/01; v.0.9.1

Alliance Semiconductor

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