MP7680 View Datasheet(PDF) - Exar Corporation
Part Name
Description
Manufacturer
MP7680 Datasheet PDF : 12 Pages
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MP7680
A1
A0
0
0
0
1
1
0
1
1
SELECTED
DAC
A
B
C
D
Table 1. DAC Selection
An 8-bit bus must use two cycles. The second cycle is
like the first one with the difference that B1/B2 = low
(Figure 5. ) During the second cycle the condition B1/B2 =
low muxes DB11-DB8 to the B2 latches (Figure 3. ).
Two important notes:
1) Timing diagrams show the inputs CS, A1, A0,
DB11-DB0 to be stable during the entire writing cycle.
In reality all the above signals can change (Figure 4. )
as long as they meet the timing conditions specified in
the Electrical Characteristic Table.
2) Only 16-bit bus cycles are shown in the next few exam-
ples of interface timing. It is possible to generate an
8-bit interface timing by replacing a single 12-bit write
cycle (Figure 4. ) with a double 8-bit write cycles
(Figure 5. ) 8-bit applications should ground inputs
DB3-DB0.
CS
A1, A0
B1/B2
DATA
WR1
High
or
to B1 & B2
High
Figure 4. 12 Bit W rite Cycle
CS
A1, A0
B1/B2
DATA
WR1
to B1
to B2
Figure 5. 8-Bit Double W rite Cycle
Rev. 3.10
XFER
WR2
or
or
DA11-0
IOUT
tS
Figure 6. Transfer Cycles from Input Latches to DAC Latches
9
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