MAX3670 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX3670

Low-Jitter 155MHz/622MHz Clock Generator

Maxim Integrated 

Low-Jitter 155MHz/622MHz

Clock Generator

Functional Diagram

R3

VCO

KVCO

C3

C1

R1

C1

R1

LOL

THADJ CTH

VC

COMP

POLAR OPAMP-

OPAMP+

REFCLK+

REFCLK-

RSEL

VSEL

VCOIN+

VCOIN-

LOL

DIV

(N3)

OPAMP

DIV

(N2)

PFD/CP

KPD

DIV

DIV

(N1)

(N2)

PECL

GAIN-CONTROL LOGIC

MAX3670

GSEL1 GSEL2 GSEL3

DIV

PECL

1/2/4/8

PSEL1 PSEL2

C2-

C2+

MOUT+

MOUT-

POUT+

POUT-

Detailed Description

The MAX3670 contains all the blocks needed to form a

PLL except for the VCO, which must be supplied sepa-

rately. The MAX3670 consists of input buffers for the ref-

erence clock and VCO, input and output clock-divider

circuitry, LOL detection circuitry, gain-control logic, a

phase-frequency detector and charge pump, an op

amp, and PECL output buffers.

This device is designed to clean up the noise on the

reference clock input and provide a low-jitter system

clock output.

Input Buffer for Reference

Clock and VCO

The MAX3670 contains differential inputs for the refer-

ence clock and the VCO. These inputs can be DC-cou-

pled and are internally biased with high impedance so

that they can be AC-coupled (Figure 1 in the Interface

Schematic section). A single-ended VCO or reference

clock can also be applied.

Input and Output Clock-Divider Circuitry

The reference clock and VCO input buffers are followed

by a pair of clock dividers that prescale the input fre-

quency of the reference clock and VCO to 77.76MHz.

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