MAX3672 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX3672

Low-Jitter 155MHz/622MHz Clock Generator

Maxim Integrated 

Low-Jitter 155MHz/622MHz Clock Generator

LOL Detection Circuitry

The MAX3672 incorporates a loss-of-lock (LOL) monitor

that consists of an XOR gate, filter, and comparator with

adjustable threshold (see the LOL Setup section). A

loss-of-lock condition is signaled with a TTL low when

the reference clock frequency differs from the VCO

frequency.

Phase-Frequency Detector and

Charge Pump

The phase-frequency detector incorporated into the

MAX3672 produces pulses proportional to the phase

difference between the reference clock and the VCO

input. The charge pump converts this pulse train to a

current signal that is fed to the op amp. The phase

detector gain can be set to either 5µA/UI or 20µA/UI

with the GSEL input (Table 4).

Op Amp

The op amp is used to form an active PLL loop filter

capable of driving the VCO control voltage input. Using

the POLAR input, the op amp input polarity can be select-

ed to work with VCOs having positive or negative gain-

transfer functions. The COMP pin selects the op amp

internal compensation. Connect COMP to ground if the

VCO control voltage is VCC referenced. Connect COMP

to VCC if the VCO control voltage is ground referenced.

Design Procedure

Setting Up the VCO and

Reference Clock

The MAX3672 accepts a range of reference clock and

VCO frequencies. The RSEL and VSEL inputs must be

set so that the output frequencies of the reference

clock and VCO pre-dividers are equal. Table 1 shows

the divider ratios and pre-divider output frequencies for

various reference clock and VCO frequencies.

Setting the Loop Bandwidth

To eliminate jitter present on the reference clock, the

proper selection of loop bandwidth is critical. If the total

output jitter is dominated by the noise at the reference

clock input, then lowering the loop bandwidth will

reduce system jitter. The loop bandwidth (K) is a func-

tion of the VCO gain (KVCO), the gain of the phase

detector (KPD), the loop filter resistor (R1), and the total

feedback-divider ratio (N = N1 ✕ N2). The loop band-

width of the MAX3672 can be approximated by:

K = KPDR1KVCO

2πN

For stability, a zero must be added to the loop in the form

of resistor R1 in series with capacitor C1 (see the

Functional Diagram). The location of the zero can be

approximated as:

fZ

=

1

2πR1C1

Because of the second-order nature of the PLL jitter

transfer, peaking will occur and is proportional to fZ/K.

For certain applications, it may be desirable to limit jitter

peaking in the PLL passband region to less than 0.1dB.

This can be achieved by setting fZ ≤ K/100.

A more detailed analysis of the loop filter is located in

application note HFDN-13.0 on www.maxim-ic.com.

Table 1. VCO and Reference Clock Setup

FVOC

(MHz)

622.08

622.08

622.08

622.08

155.52

155.52

155.52

155.52

FREF

(MHz)

622.08

155.52

77.76

19.44

622.08

155.52

77.76

19.44

VSEL INPUT

OPEN

OPEN

OPEN

GND

—

OPEN

VCC

OPEN

VCO

DIVIDER N1

8

8

8

32

—

8

4

8

RSEL

INPUT

GND

OPEN

VCC

VCC

—

GND

OPEN

VCC

REFERENCE-

CLOCK DIVIDER N3

PRE-DIVIDER

OUTPUT FREQUENCY

(MHz)

8

77.76

2

77.76

1

77.76

1

19.44

—

––

8

19.44

2

38.88

1

19.44

8 _______________________________________________________________________________________

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