MC13783 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
MC13783 Datasheet PDF : 50 Pages
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Functional Description
4.1.1.2 Register Set
The register set is given in Table 5.
Register
0
Interrupt Status 0
16
1
Interrupt Mask 0
17
2
Interrupt Sense 0
18
3
Interrupt Status 1
19
4
Interrupt Mask 1
20
5
Interrupt Sense 1
21
6
Power Up Mode Sense
22
7
Identification
23
8
Semaphore
24
9
Arbitration Peripheral Audio
25
10 Arbitration Switchers
26
11 Arbitration Regulators 0
27
12 Arbitration Regulators 1
28
13 Power Control 0
29
14 Power Control 1
30
15 Power Control 2
31
Table 5. Register Set
Register
Regen Assignment
Control Spare
Memory A
Memory B
RTC Time
RTC Alarm
RTC Day
RTC Day Alarm
Switchers 0
Switchers 1
Switchers 2
Switchers 3
Switchers 4
Switchers 5
Regulator Setting 0
Regulator Setting 1
Register
32 Regulator Mode 0
33 Regulator Mode 1
34 Power Miscellaneous
35 Power Spare
36 Audio Rx 0
37 Audio Rx 1
38 Audio Tx
39 SSI Network
40 Audio Codec
41 Audio Stereo DAC
42 Audio Spare
43 ADC 0
44 ADC 1
45 ADC 2
46 ADC 3
47 ADC 4
Register
48 Charger
49 USB 0
50 Charger USB 1
51 LED Control 0
52 LED Control 1
53 LED Control 2
54 LED Control 3
55 LED Control 4
56 LED Control 5
57 Spare
58 Trim 0
59 Trim 1
60 Test 0
61 Test 1
62 Test 2
63 Test 3
4.1.1.3 Interface Requirements
4.1.1.3.1 SPI Interface Description
The operation of both SPI interfaces is equivalent. Therefore, all SPI bus names without prefix PRI or SEC
correspond to both the PRISPI and SECSPI interfaces.
The control bits are organized into 64 fields. Each of these 64 fields contains 32 bits. A maximum of 24
data bits is used per field. In addition, there is one “dead” bit between the data and address fields. The
remaining bits include 6 address bits to address the 64 data fields and one write enable bit to select whether
the SPI transaction is a read or a write.
For each SPI transfer, first a one is written to the read/write bit if this SPI transfer is to be a write. A zero
is written to the read/write bit if this is to be a read command only. If a zero is written, then any data sent
after the address bits are ignored and the internal contents of the field addressed do not change when the
32nd CLK is sent. Next the 6-bit address is written, MSB first. Finally, data bits are written, MSB first.
Once all the data bits are written then the data is transferred into the actual registers on the falling edge of
the 32nd CLK.
MC13783 Technical Data, Rev. 3.5
18
Freescale Semiconductor
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