MC13783 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MC13783

Power Management and Audio Circuit

Freescale Semiconductor 

Functional Description

The default CS polarity is active high. The CS line must remain active during the entire SPI transfer. In

case the CS line goes inactive during a SPI transfer all data is ignored. To start a new SPI transfer, the CS

line must go inactive and then go active again. The MISO line will be tri-stated while CS is low.

Note that not all bits are truly writable. Refer to the individual subcircuit descriptions to determine the

read/write capability of each bit. All unused SPI bits in each register must be written to a zero. SPI

readbacks of the address field and unused bits are returned as zero. To read a field of data, the MISO pin

will output the data field pointed to by the 6 address bits loaded at the beginning of the SPI sequence.

CS

CLK

MOSI

Write_En

Address5

Address4

Address3

Address2

Address 1

Address 0

“Dead Bit”

Data 23

Data 22

Data 1

Data 0

MISO

Data 23

Data 22

Data 1

Data 0

Figure 2. SPI Transfer Protocol Single Read/Write Access

CS

MOSI

Preamble First Address

24 Bits Data

Preamble Another Address

24 Bits Data

MISO

24 Bits Data

24 Bits Data

Figure 3. SPI Transfer Protocol Multiple Read/Write Access

4.1.1.3.2 SPI Requirements

The requirements for both SPI interfaces are equivalent. Therefore, all SPI bus names without prefix PRI

or SEC correspond to both SPI interfaces. The below diagram and table summarize the SPI electrical and

timing requirements. The SPI input and output levels are set independently via the PRIVCC and SECVCC

pins by connecting those to the proper supply.

MC13783 Technical Data, Rev. 3.5

Freescale Semiconductor

19

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