Freescale Semiconductor, Inc.
Timing Diagrams
CS
SCLK
DI
0.2 VDD
tLEAD
0.7 VDD
0.2 VDD
tDI(SU) tDI(HOLD)
0.7 VDD
0.2 VDD
MSB in
DO
tDO(EN)
0.7 VDD
0.2 VDD
MSB out
tVALID
Figure 2. SPI Timing Diagram
tLAG
tDO(DIS)
LSB out
SCLK
VDD = 5.0 V
33880
Under
Test
DO
CL = 200 pF
NOTE: CL represents the total capacitance of the test
fixture and probe.
Figure 3. Valid Data Delay Time and Valid Time Test Circuit
VDD = 5.0 V
VPull-Up = 2.5 V
33880
CS
Under
Test
RL = 1.0 kΩ
DO
CL = 200 pF
NOTE: CL represents the total capacitance of the test
fixture and probe.
Figure 4. Enable and Disable Time Test Circuit
33880
12
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