MC33880DW View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MC33880DW Datasheet PDF : 24 Pages
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Freescale Semiconductor, Inc.
SPI Integrity Check
It is recommended that one check the integrity of the SPI
communication with the initial power-up of the VDD and EN pins.
After initial system start-up or reset, the MCU will write one
16-bit pattern to the 33880. The first eight bits read by the MCU
will be the fault status of the outputs, while the second eight bits
will be the first byte of the bit pattern. Bus integrity is confirmed
by the MCU receiving the same bit pattern it sent. Please note
that the second byte the MCU sends to the device is the
command byte and will be transferred to the outputs with rising
edge of CS.
Overtemperature Fault
Overtemperature detect and shutdown circuits are
specifically incorporated for each individual output. The
shutdown following an overtemperature condition is
independent of the system clock or any other logic signal. Each
independent output shuts down at 155°C to 185°C. When an
output shuts down due to an overtemperature fault, no other
outputs are affected. The MCU recognizes the fault by a one in
the fault status register. After the 33880 device has cooled
below the switch point temperature and 15°C hysteresis, the
output will activate unless told otherwise by the MCU via SPI to
shut down.
Overvoltage Fault
An overvoltage condition on the VPWR pin will cause the
device to shut down all outputs until the overvoltage condition
is removed. When the overvoltage condition is removed, the
outputs will resume their previous state. This device does not
detect an overvoltage on the VDD pin. The overvoltage
threshold on the VPWR pin is specified as 25 V to 30 V with
1.0 V typical hysteresis. A VPWR overvoltage detect is global,
causing all outputs to be turned OFF.
Output OFF Open Load Fault
An output OFF open load fault is the detection and reporting
of an open load when the corresponding output is disabled
(input bit programmed to a logic low state). The output OFF
open load fault is detected by comparing the drain-to-source
voltage of the specific MOSFET output to an internally
generated reference. Each output has one dedicated
comparator for this purpose.
An output off open load fault is indicated when the drain-to-
source voltage is less than the output threshold voltage
(VTHRES) of 1.0 V to 3.0 V. Hence, the 33880 will declare the
load open in the OFF state when the VDS is less than 1.0 V.
This device has an internal 650 µA current source connected
from drain to source of the output MOSFET. This prevents
either configuration of the driver from having a floating output.
To achieve low sleep mode quiescent currents, the open load
detect current source of each driver is switched off when VDD is
removed.
During output switching, especially with capacitive loads, a
false output OFF open load fault may be triggered. To prevent
this false fault from being reported, an internal fault filter of
100 µs to 300 µs is incorporated. A false fault reporting is a
function of the load impedance, RDS(ON), COUT of the MOSFET,
as well as the supply voltage, VPWR. The rising edge of CS
triggers the built-in fault delay timer. The timer will time out
before the fault comparator is enabled and the fault is detected.
Once the condition causing the open load fault is removed, the
device will resume normal operation. The open load fault
however, will be latched in the output DO register for the MCU
to read.
Shorted Load Fault
A shorted load (overcurrent) fault can be caused by any
output being shorted directly to supply or an output causing the
device to current limit (linear short).
There are two safety circuits progressively in operation
during load short conditions providing system protection:
1. The device’s output current is monitored in an analog
fashion using SENSEFET approach and current
limited.
2. The device’s output thermal limit is sensed and when
attained causes only the specific faulted output to shut
down. The output will remain off until cooled. The device
will then reassert the output automatically. The cycle will
continue until the fault is remove or the command bit
instructs the output off.
Undervoltage Shutdown
An undervoltage VDD condition will result in the global
shutdown of all outputs. The undervoltage threshold is between
3.9 V and 4.6 V. When VDD goes below the threshold, all
outputs are turned OFF and the Fault Status (FS) register is
cleared. As VDD returns to normal levels, the FS register will
resume normal operation.
An undervoltage condition at the VPWR pin will not cause
output shutdown and reset. When VPWR is between 5.5 V and
9.0 V, the output will operate per the command word. However,
the status as reported by the serial data output (DO) pin may
not be accurate below 9.0 V VPWR. Proper operation at VPWR
voltages below 5.5 V cannot be guaranteed.
33880
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