56F8356 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
56F8356 Datasheet PDF : 160 Pages
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Freescale Semiconductor, Inc.
56F8356 Signal Pins
Table 2-2 56F8356 Signal and Package Information for the 144-Pin LQFP
Signal Name Pin No. Type
D15
137
Input/
Output
State
During
Reset
Tri-stated
Signal Description
Data Bus — D15 specifies part of the data for external
program or data memory accesses.
(GPIOF8)
Input/
Output
Input
Port F GPIO — This GPIO pin can be individually
programmed as an input or output pin.
At reset, this pin defaults to the data bus function.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOF_PUR register.
RD
45
Output Tri-stated Read Enable — RD is asserted during external memory
read cycles. When RD is asserted low, pins D0 - D15
become inputs and an external device is enabled onto the
data bus. When RD is deasserted high, the external data is
latched inside the device. When RD is asserted, it qualifies
the A0 - A16, PS, DS, and CSn pins. RD can be connected
directly to the OE pin of a Static RAM or ROM.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), RD is tri-stated when the external bus
is inactive.
To deactivate the internal pull-up resistor, set the CTRL bit
in the SIM_PUDR register.
WR
44
Output Tri-stated Write Enable — WR is asserted during external memory
write cycles. When WR is asserted low, pins D0 - D15
become outputs and the device puts data on the bus.
When WR is deasserted high, the external data is latched
inside the external device. When WR is asserted, it
qualifies the A0 - A16, PS, DS, and CSn pins. WR can be
connected directly to the WE pin of a static RAM.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), WR is tri-stated when the external bus
is inactive.
To deactivate the internal pull-up resistor, set the CTRL bit
in the SIM_PUDR register.
56F8356 Technical Data
19
Preliminary
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