MC68322 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MC68322

Integrated Printer Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

Signal Name

Test

Transfer Acknowledge

Video

Video Clock

Wait

Write Enable

Write Enable – Lower

Write Enable – Upper

Table 1. Signal Index (Continued)

Mnemonic

Function

TEST

ACK

VIDEO

VCLK

WAIT

WE

WRL

Test mode pin.

Parallel port transfer acknowledge.

Video is the digital serial video image.

Video clock is used to shift the video image.

PROM and I/O wait.

DRAM write enable strobe.

PROM and I/O write enable strobe indicates valid data on D7–D0.

WRU

PROM and I/O write enable strobe indicates valid data on D15–D8.

TERMS AND DEFINITIONS

BANDING

Banding is the process of building an image out of strips called bands. These bands, which describe the

graphics operations necessary to construct the bit-mapped image for the page, are represented in an

intermediate form called a display list. The printer display language (PDL) emulator firmware running on the

EC000 Core generates the display list before the print engine begins the actual printing process. Generally,

band n + 1 is being composed while band n is being output to the print engine.

Banding is desirable in printer controllers because the resulting system cost can be greatly reduced due to

the significant memory savings associated with this technique. For banding to be viable, the display list must

meet two requirements: it must fit in considerably less memory than the full-page image would require and

the commands required to generate a band (called graphic orders) must be executable within the time it

takes to print the previous band.

RUN-LENGTH ENCODING (RLE)

The scanline graphics orders contained within the display list reference a set of associated tables located in

memory. These scanline tables contain bitstring specifiers that are run-length encoded in order to

characterize an extremely compact representation of a bit-mapped image. The combination of run length

compressed graphics data and the elimination of redundant information in the display list enables the

display list to be significantly smaller than the actual bit-mapped image.

EC000 CORE PROCESSOR UNIT

The EC000 Core is a static, low-power, 32-bit general purpose microprocessor. It has a 28-bit address

range for internal register decoding of chip selects and DRAM controller functions. This address range

allows for full code compatibility with existing M68000 family based designs and future upward compatibility

to higher performance designs. The EC000 Core is register and memory map compatible with the industry

standard MC68000 and MC68HC000 processors.

The EC000 Core performs general purpose computing, I/O handling, exception handling, and display list

rendering. For more information about the EC000 Core, refer to the MC68322 User's Manual.

The MC68322 was designed to support EC000 Core in-circuit emulation so that new hardware and software

designs, which are being ported to the MC68322, can be tested rapidly. This is accomplished by providing

additional signals in a 208-pin pin grid array (PGA) package that are not available in the 160-pin quad flat

pack (QFP) package.

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MC68322 PRODUCT INFORMATION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

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