MCF5253 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MCF5253

ColdFire® Microprocessor Data Sheet

Freescale Semiconductor 

Electrical Specifications

Figure 2 and Table 10 provide the clock timing diagram and timing parameters.

CRIN

PSTCLK

BCLK

C5

C6

C6

C7

C8

C8

Figure 2. Clock Timing Definition

NOTE

Signals shown in Figure 2 are in relation to the SYSCLK clock. No

relationship between signals is implied or intended.

Table 10. Clock Timing Parameters

ID

Characteristic

– CRIN Frequency with external oscillator

– CRIN Frequency with internal oscillator

C5 PSTCLK cycle time

C6 PSTCLK duty cycle

C7 BCLK cycle time

C8 BCLK duty cycle

140 MHz CPU

Min Max

5.00 33.86

5

16.94

7

–

40

60

14.0

–

35

65

Units

MHz

MHz

ns

%

ns

%

4.1 SDRAM Bus Timing

The SDRAM bus is a synchronous bus. Propagation delays, set-up times and hold times with respect to

the SDRAM clock BCLK are shown in Figure 3 and the parameters provided in Table 11. When BCLK

clock is not active, SDRAM interface is not valid and the external bus cannot be used.

MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 2

14

Freescale Semiconductor

Share Link: