MCF5253 View Datasheet(PDF) - Freescale Semiconductor
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Description
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MCF5253 Datasheet PDF : 32 Pages
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Electrical Specifications
Table 12. SPDIF Propagation Skew and Transition Parameters
Characteristic
Pin Load
Prop Delay
Maximum
Skew1
Maximum
Transition2 Rise
Maximum
Transition Fall
Maximum
Units
EBUIN1, EBUIN2, EBUIN3, EBUIN4:
–
–
0.7
–
asynchronous inputs, no specs apply
EBUOUT1, EBUOUT2 output
40 pF
–
1.5
24.2
EBUOUT1, EBUOUT2 output
20 pF
–
1.5
13.6
1 Skew value does not include the skew introduced by different rise and fall times.
2 Transition times between 10% Vdd and 90% Vdd.
–
ns
31.3
ns
18.0
ns
4.3 Serial Audio Interface Timing
The Serial Audio Interface fully complies with the Industry standard Philips IIS (InterIC Serial Audio Bus)
timings.
4.4 DDATA/PST/PSTCLK Debug Interface
Table 13 provides the timing parameters.
Table 13. DDATA/PST/PSTCLK Debug Interface Timing Parameters
Characteristic
Pin Load
Min
Max
Units
PSTCLK clock rise edge to DDATA/PSTDATA1 invalid
PSTCLK clock rise edge to DDATA/PSTDATA2 valid
15 pF
–1.0
—
ns
15 pF
—
4.0
ns
1 Note that output data may go invalid before rising edge of the clock. To clock data in reliably, you need to sample data, for
example, 2 ns before rising edge of clock.
2 Timing figure given takes 50% margin for noise and uncertainty on pin capacitance. Simulated clock-to-data, not taking noise
effects into account is 2.7 ns.
4.5 BDM and JTAG Timing
Table 14 provides the BDM timing parameters.
Table 14. BDM Interface Timing Parameters
Characteristic
Min
Max
Clock period for DSCLK clock
—
5T1
Set-up time DSI, BKPT, to DSCLK rising edge
4.0
—
Hold time DSI, BKPT to DSCLK rising edge
—
T+ 4.0
Propagation delay DSCLK rising edge to TDO/DSO change
3T
4T + 32
1 T denotes the CPU clock period. E.g. if the CPU is running at 100 MHz, T = 10 ns
Units
ns
ns
ns
ns
Figure 4 provides the JTAG timing diagram and Table 15 provides the JTAG timing parameters.
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 2
16
Freescale Semiconductor
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