MPC8544E(2009) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8544E
(Rev.:2009)

PowerQUICC™ III Integrated Processor Hardware Specifications

Freescale Semiconductor 

System Design Information

using only the TCK and TMS signals, generally systems will assert TRST during the power-on reset flow.

Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the

common on-chip processor (COP) function.

The COP function of these processors allow a remote computer system (typically, a PC with dedicated

hardware and debugging software) to access and control the internal operations of the processor. The COP

interface connects primarily through the JTAG port of the processor, with some additional status

monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order

to fully control the processor. If the target system has independent reset sources, such as voltage monitors,

watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be

merged into these signals with logic. The arrangement shown in Figure 69 allows the COP port to

independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well.

The COP interface has a standard header, shown in Figure 68, for connection to the target system, and is

based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The

connector typically has pin 14 removed as a connector key.

The COP header adds many benefits such as breakpoints, watchpoints, register and memory

examination/modification, and other standard debugger features. An inexpensive option can be to leave

the COP header unpopulated until needed.

There is no standardized way to number the COP header; consequently, many different pin numbers have

been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others

use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as

with an IC). Regardless of the numbering, the signal placement recommended in Figure 68 is common to

all known emulators.

21.9.1 Termination of Unused Signals

If the JTAG interface and COP header will not be used, Freescale recommends the following connections:

• TRST should be tied to HRESET through a 0-kΩ isolation resistor so that it is asserted when the

system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during

the power-on reset flow. Freescale recommends that the COP header be designed into the system

as shown in Figure 69. If this is not possible, the isolation resistor will allow future access to TRST

in case a JTAG interface may need to be wired onto the system in future debug situations.

• No pull-up/pull-down is required for TDI, TMS, or TDO.

MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

112

Freescale Semiconductor

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