MSM7654 View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
Manufacturer
MSM7654 Datasheet PDF : 53 Pages
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¡ Semiconductor
MSM7654
3) I2C-bus Interface Input/Output Timing
When writing to internal registers, written contents are set to the internal registers MR1 [7] and
CR0 [2:1] during the vertical blanking period. On the other hand, written contents are
immediately set to the other internal registers.
(Note) Data cannot be changed when SCL is "H". Data line can be changed only when SCL is
"L".
The I2C-bus Interface Basic Input/Output Timing is shown below.
I2C-bus AC Characteristics
Parameter
I2C-bus Clock Cycle Time
I2C-bus High Level Cycle
I2C-bus Low Level Cycle
SDA-SCL Overlap Time
Symbol
tC_SCL
tH_SCL
tL_SCL
tOV
(Ta = 0 to 70°C, DVDD = 3.3 V ±0.3 V, AVDD = 3.3 V ±0.3 V)
Condition
Min. Typ. Max. Unit
Rpull_up = 4.7 kW
200
—
—
ns
Rpull_up = 4.7 kW
100
—
—
ns
Rpull_up = 4.7 kW
100
—
—
ns
Rpull_up = 4.7 kW
40
—
—
ns
tOV
SDA
MSB
SCL
S
1
2
Start Condition
7
8
9
ACK
Data Line Stable: Data Valid Change of Data Allowed
tC_SCL
1
2
9
3-8
ACK
tL_SCL
tH_SCL
P
Stop Condition
I2C-bus Input/Output Basic Timing
4) Reset Input Timing
The reset timing is asynchronous with the clock timing.
Reset AC Characteristics
Parameter
Minimum Reset Pulse Width
Symbol
tW2
(Ta = 0 to 70°C, DVDD = 3.3 V ±0.3 V, AVDD = 3.3 V ±0.3 V)
Condition
Min. Typ. Max. Unit
—
81.5
—
—
ns
CLKX2 (Input)
RESET-L (Input)
tW2
Reset Timing
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