MT48LC2M32B2 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC2M32B2

SYNCHRONOUS DRAM

Micron Technology 

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate either fixed-length or full-page bursts. The most

recently registered READ or WRITE command prior to

the BURST TERMINATE command will be truncated,

as shown in the Operation section of this data sheet.

AUTO REFRESH

AUTO REFRESH is used during normal operation of

the SDRAM and is analagous to CAS#-BEFORE-RAS#

(CBR) REFRESH in conventional DRAMs. This com-

mand is nonpersistent, so it must be issued each time

a refresh is required.

The addressing is generated by the internal refresh

controller. This makes the address bits “Don’t Care”

during an AUTO REFRESH command. The 64Mb

SDRAM requires 4,096 AUTO REFRESH cycles every

64ms (tREF), regardless of width option. Providing a

distributed AUTO REFRESH command every 15.625µs

will meet the refresh requirement and ensure that each

row is refreshed. Alternatively, 4,096 AUTO REFRESH

commands can be issued in a burst at the minimum

cycle rate (tRC), once every 64ms.

64Mb: x32

SDRAM

SELF REFRESH

The SELF REFRESH command can be used to retain

data in the SDRAM, even if the rest of the system is

powered down. When in the self refresh mode, the

SDRAM retains data without external clocking. The SELF

REFRESH command is initiated like an AUTO REFRESH

command except CKE is disabled (LOW). Once the SELF

REFRESH command is registered, all the inputs to the

SDRAM become “Don’t Care” with the exception of

CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM pro-

vides its own internal clocking, causing it to perform its

own AUTO REFRESH cycles. The SDRAM must remain

in self refresh mode for a minimum period equal to

tRAS and may remain in self refresh mode for an indefi-

nite period beyond that.

The procedure for exiting self refresh requires a se-

quence of commands. First, CLK must be stable (stable

clock is defined as a signal cycling within timing con-

straints specified for the clock pin) prior to CKE going

back HIGH. Once CKE is HIGH, the SDRAM must have

NOP commands issued (a minimum of two clocks) for

tXSR because time is required for the completion of any

internal refresh in progress.

Upon exiting SELF REFRESH mode, AUTO REFRESH

commands must be issued every 15.625ms or less as

both SELF REFRESH and AUTO REFRESH utililze the

row refresh counter.

64Mb: x32 SDRAM

64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02

11

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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